From patchwork Thu Aug 17 18:16:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 13356865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F2DFC3DA6C for ; Thu, 17 Aug 2023 18:21:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=3LZqrDM37yEYQUZ0grDwaxJSzyYx0lGcwVw5eT396Vs=; b=qchiGnR9nYKxlL7Q8P1Qlpk2lC GOfIJH3UotYV46+S5AzBJ2azgyqI/0aTTikYpXDLQP0FC1ZrWdZ4sfJFED1v0kJ2zhJJdDNHmABI4 mMcq/HeHcanIYLlABVh0fNOg3KZWmi79bkIvuefPag7qmgyAuDXU3Avq0Rh5UUAOxDGjVpYkTmjW0 K+3iIcCTZwK/W/ZYoALg+7J2NkjOCwFLRY3IpSeGOWiPjzNhPj4z0Snc+9jfsp2ZZutrT2888Bfg6 PJ4ZrRsnhnGf5SaOML7mSux3a+V7laHKj4QHmSURezAkurOPL5xvookGUMQDeelR58Ek7vrxjdi7s yw5EWdVQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qWhcm-006xT6-2z; Thu, 17 Aug 2023 18:21:36 +0000 Received: from mail-yw1-x114a.google.com ([2607:f8b0:4864:20::114a]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qWhce-006xPt-1j for linux-arm-kernel@lists.infradead.org; Thu, 17 Aug 2023 18:21:30 +0000 Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-58c561f4ac3so1232097b3.2 for ; Thu, 17 Aug 2023 11:21:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1692296487; x=1692901287; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=UbN8hteG6YSwFJxRxYYT0MEpu8iWEUW9NUmuxxHFuvs=; b=V/qRRHg6MxCpJtqxo3ZVdjG1rtcfb3VN30OZkf2bYzKnf1dwUQpDRAbgJHRa1W4GPN GeC8ir3P3lkFNpMfTUdMMn0ETUtjNTn5bpC6uHjzkLIQ0OO7K2xEyO9eo3ZfyRAVAyyL CIYUQQujP3AWaXOBHYklLLP5lTjXPJMgOhcJhA7ZvQB0qe5P8EY1w2SdL9SIJzdaDMkb Um/na90xfIJIGQlpGgHYR0JestTgRSFW6fO7IqDjCnoTFwky6qgBC6W4ZCk/hwSxPQCS bkcSuWBUJOZqHYvAYH4tvk6Qc/YUA5NJnp5dW6V9ZNs4O0ULt5x9B/CQRhmeh8ZJTQE/ XKxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692296487; x=1692901287; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=UbN8hteG6YSwFJxRxYYT0MEpu8iWEUW9NUmuxxHFuvs=; b=aXo6ai1Fg1O8gAUjDX7tHPw6dlKmkD/U+zXrs5PAnI1nB8rWJ1e3Ran9i1xZYVTik4 iY79E5Uah3XvlKLmgNeFN1qXqE+M8wX+zdypMMC7RipcubYTtwoAmE9pvZsM+MQ62FdM 0024BzmdBUFbZzwysuDiDeuT2lVTp8m9uXfUM6Sx7TJqwkWaL5gQXvrq7bOOUeOAXmlg bd/0kWFAtQpK4Rv+B2k0JIxycEwfPW+u/y6Ee7mj+aW5K7MBCmio0NwfM0AiwU02wFLz MZygTtUFeAjR1TX8DX+JjEGsS301fchoB1abXfS+Em9aoHJ6MC0uPrSGe+LkuPWo85q4 cHxQ== X-Gm-Message-State: AOJu0YzgxZ4tATmMThFxMFXF3yTJBdr0VMkpH7rEoJH0j9rxcquks+X8 NoCj8efIymTc2vC1SUYHd4JWkt2JZTX9 X-Google-Smtp-Source: AGHT+IGTAACVuz6ZInq7S1tmwe0PZqsqwSGF8b8sGnN43WrsM/3yciEvcFsY+UaDmtHr5pX+49suRdb9CKv9 X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:4a77:fd20:7069:bdf9]) (user=mshavit job=sendgmr) by 2002:a05:6902:168a:b0:d49:e117:3a17 with SMTP id bx10-20020a056902168a00b00d49e1173a17mr6554ybb.4.1692296487005; Thu, 17 Aug 2023 11:21:27 -0700 (PDT) Date: Fri, 18 Aug 2023 02:16:26 +0800 In-Reply-To: <20230817182055.1770180-1-mshavit@google.com> Mime-Version: 1.0 References: <20230817182055.1770180-1-mshavit@google.com> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog Message-ID: <20230818021629.RFC.v1.4.I100c49a1e2ce915982965a065f95a494c2e9ad28@changeid> Subject: [RFC PATCH v1 4/8] iommu/arm-smmu-v3: check smmu compatibility on attach From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, jgg@nvidia.com, nicolinc@nvidia.com, tina.zhang@intel.com, jean-philippe@linaro.org, robin.murphy@arm.com, Michael Shavit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230817_112128_571455_1295F636 X-CRM114-Status: GOOD ( 20.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Record the domain's pgtbl_cfg when it's being prepared so that it can later be compared to the features an smmu supports. Verify a domain's compatibility with the smmu when it's being attached to a master belong to a different smmu device. Signed-off-by: Michael Shavit --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 103 ++++++++++++++++---- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 + 2 files changed, 86 insertions(+), 19 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 447af74dbe280..c0943cf3c09ca 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2195,17 +2195,48 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, return 0; } +static int arm_smmu_prepare_pgtbl_cfg(struct arm_smmu_device *smmu, + enum arm_smmu_domain_stage stage, + struct io_pgtable_cfg *pgtbl_cfg) +{ + unsigned long ias, oas; + + switch (stage) { + case ARM_SMMU_DOMAIN_S1: + ias = (smmu->features & ARM_SMMU_FEAT_VAX) ? 52 : 48; + ias = min_t(unsigned long, ias, VA_BITS); + oas = smmu->ias; + break; + case ARM_SMMU_DOMAIN_NESTED: + case ARM_SMMU_DOMAIN_S2: + ias = smmu->ias; + oas = smmu->oas; + break; + default: + return -EINVAL; + } + + *pgtbl_cfg = (struct io_pgtable_cfg) { + .pgsize_bitmap = smmu->pgsize_bitmap, + .ias = ias, + .oas = oas, + .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENCY, + .tlb = &arm_smmu_flush_ops, + .iommu_dev = smmu->dev, + }; + return 0; +} + static int arm_smmu_domain_finalise(struct iommu_domain *domain) { int ret; - unsigned long ias, oas; enum io_pgtable_fmt fmt; - struct io_pgtable_cfg pgtbl_cfg; struct io_pgtable_ops *pgtbl_ops; int (*finalise_stage_fn)(struct arm_smmu_domain *, struct io_pgtable_cfg *); struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu = smmu_domain->smmu; + struct io_pgtable_cfg *pgtbl_cfg = &smmu_domain->pgtbl_cfg; if (domain->type == IOMMU_DOMAIN_IDENTITY) { smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS; @@ -2220,16 +2251,11 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain) switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_S1: - ias = (smmu->features & ARM_SMMU_FEAT_VAX) ? 52 : 48; - ias = min_t(unsigned long, ias, VA_BITS); - oas = smmu->ias; fmt = ARM_64_LPAE_S1; finalise_stage_fn = arm_smmu_domain_finalise_s1; break; case ARM_SMMU_DOMAIN_NESTED: case ARM_SMMU_DOMAIN_S2: - ias = smmu->ias; - oas = smmu->oas; fmt = ARM_64_LPAE_S2; finalise_stage_fn = arm_smmu_domain_finalise_s2; break; @@ -2237,24 +2263,19 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain) return -EINVAL; } - pgtbl_cfg = (struct io_pgtable_cfg) { - .pgsize_bitmap = smmu->pgsize_bitmap, - .ias = ias, - .oas = oas, - .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENCY, - .tlb = &arm_smmu_flush_ops, - .iommu_dev = smmu->dev, - }; + ret = arm_smmu_prepare_pgtbl_cfg(smmu, smmu_domain->stage, pgtbl_cfg); + if (ret) + return ret; - pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); + pgtbl_ops = alloc_io_pgtable_ops(fmt, pgtbl_cfg, smmu_domain); if (!pgtbl_ops) return -ENOMEM; - domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; - domain->geometry.aperture_end = (1UL << pgtbl_cfg.ias) - 1; + domain->pgsize_bitmap = pgtbl_cfg->pgsize_bitmap; + domain->geometry.aperture_end = (1UL << pgtbl_cfg->ias) - 1; domain->geometry.force_aperture = true; - ret = finalise_stage_fn(smmu_domain, &pgtbl_cfg); + ret = finalise_stage_fn(smmu_domain, pgtbl_cfg); if (ret < 0) { free_io_pgtable_ops(pgtbl_ops); return ret; @@ -2406,6 +2427,46 @@ static void arm_smmu_disable_pasid(struct arm_smmu_master *master) pci_disable_pasid(pdev); } +static int +arm_smmu_verify_domain_compatible(struct arm_smmu_device *smmu, + struct arm_smmu_domain *smmu_domain) +{ + struct io_pgtable_cfg pgtbl_cfg; + int ret; + + if (smmu_domain->domain.type == IOMMU_DOMAIN_IDENTITY) + return 0; + + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) { + if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) + return -EINVAL; + if (smmu_domain->s2_cfg.vmid >> smmu->vmid_bits) + return -EINVAL; + } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) + return -EINVAL; + if (smmu_domain->cd.asid >> smmu->asid_bits) + return -EINVAL; + } + + ret = arm_smmu_prepare_pgtbl_cfg(smmu, smmu_domain->stage, &pgtbl_cfg); + if (ret) + return ret; + + if (smmu_domain->pgtbl_cfg.ias > pgtbl_cfg.ias || + smmu_domain->pgtbl_cfg.oas > pgtbl_cfg.oas || + /* + * The supported pgsize_bitmap must be a superset of the domain's + * pgsize_bitmap. + */ + (smmu_domain->pgtbl_cfg.pgsize_bitmap ^ pgtbl_cfg.pgsize_bitmap) & + smmu_domain->pgtbl_cfg.pgsize_bitmap || + smmu_domain->pgtbl_cfg.coherent_walk != pgtbl_cfg.coherent_walk) + return -EINVAL; + + return 0; +} + static void arm_smmu_installed_smmus_remove_device( struct arm_smmu_domain *smmu_domain, struct arm_smmu_master *master) @@ -2449,6 +2510,10 @@ arm_smmu_installed_smmus_add_device(struct arm_smmu_domain *smmu_domain, } } if (!list_entry_found) { + ret = arm_smmu_verify_domain_compatible(smmu, smmu_domain); + if (ret) + goto unlock; + installed_smmu = kzalloc(sizeof(*installed_smmu), GFP_KERNEL); if (!installed_smmu) { ret = -ENOMEM; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 2ab23139c796e..143b287be2f8b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -9,6 +9,7 @@ #define _ARM_SMMU_V3_H #include +#include #include #include #include @@ -729,6 +730,7 @@ struct arm_smmu_domain { struct mutex init_mutex; /* Protects smmu pointer */ struct io_pgtable_ops *pgtbl_ops; + struct io_pgtable_cfg pgtbl_cfg; atomic_t nr_ats_masters; enum arm_smmu_domain_stage stage;