| Message ID | 20230819105002.132750-1-aford173@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [V3,1/2] arm64: dts: imx8mp: Fix SDMA2/3 clocks | expand |
On Sat, Aug 19, 2023 at 05:50:01AM -0500, Adam Ford wrote: > Commit 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks > from CCM node") removed the Audio clocks from the main clock node, because > the intent is to force people to setup the audio PLL clocks per board > instead of having a common set of rates, since not all boards may use > the various audio PLL clocks in the same way. > > Unfortunately, with this parenting removed, the SDMA2 and SDMA3 > clocks were slowed to 24MHz because the SDMA2/3 clocks are controlled > via the audio_blk_ctrl which is clocked from IMX8MP_CLK_AUDIO_ROOT, > and that clock is enabled by pgc_audio. > > Per the TRM, "The SDMA2/3 target frequency is 400MHz IPG and 400MHz > AHB, always 1:1 mode, to make sure there is enough throughput for all > the audio use cases." > > Instead of cluttering the clock node, place the clock rate and parent > information into the pgc_audio node. > > With the parenting and clock rates restored for IMX8MP_CLK_AUDIO_AHB, > and IMX8MP_CLK_AUDIO_AXI_SRC, it appears the SDMA2 and SDMA3 run at > 400MHz again. > > Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node") > Signed-off-by: Adam Ford <aford173@gmail.com> > Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > Reviewed-by: Fabio Estevam <festevam@gmail.com> Applied both, thanks!
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 6f2f50e1639c..83d907294fbc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -790,6 +790,12 @@ pgc_audio: power-domain@5 { reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, <&clk IMX8MP_CLK_AUDIO_AXI>; + assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>, + <600000000>; }; pgc_gpu2d: power-domain@6 {
Commit 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node") removed the Audio clocks from the main clock node, because the intent is to force people to setup the audio PLL clocks per board instead of having a common set of rates, since not all boards may use the various audio PLL clocks in the same way. Unfortunately, with this parenting removed, the SDMA2 and SDMA3 clocks were slowed to 24MHz because the SDMA2/3 clocks are controlled via the audio_blk_ctrl which is clocked from IMX8MP_CLK_AUDIO_ROOT, and that clock is enabled by pgc_audio. Per the TRM, "The SDMA2/3 target frequency is 400MHz IPG and 400MHz AHB, always 1:1 mode, to make sure there is enough throughput for all the audio use cases." Instead of cluttering the clock node, place the clock rate and parent information into the pgc_audio node. With the parenting and clock rates restored for IMX8MP_CLK_AUDIO_AHB, and IMX8MP_CLK_AUDIO_AXI_SRC, it appears the SDMA2 and SDMA3 run at 400MHz again. Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> --- V3: Update commit message wording. No functional change V2: Slow AUDIO_AXI to 600MHz for nominal drive. Individual boards can increase this to 800MHz if they have the proper voltage configured.