From patchwork Mon Aug 21 21:22:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13359831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81BB5EE49A0 for ; Mon, 21 Aug 2023 21:23:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=zlZ70z60XtttGFaWGV9fQgKt47PRZOdGjut6GBgYDOs=; b=rsdy3z4nzKlXG5FOiVrr1i9J4B CGz6uuj4sySzjuKzk8Ro++0uoboRmjAO53f2btq721+wJDoORoE9fJcJEEcH5Nmkukc2ZBSPTdW/a rOD6ewcYsqBy/zm2MdxVlBfOPFqbhPbVh+n25c4w8an/3MGu/CvY/e9ECdcNpkLx6miPRFW29ePy5 i2D1d66Ym1200F3sJu07BkREr46lmjTtu/yhorPKLzlGlYXg1HNwh+txk9OYppy7ca4kFSMiqOBnV WxeWQP9rO4pc794KMZNzDt/5G5807YBoMGWjI0KjPQTojMIBKrNZ63QQP8iQX/pvmeB4wne3GQjWS TYKqMWJw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qYCMr-00EiQz-18; Mon, 21 Aug 2023 21:23:21 +0000 Received: from mail-pg1-x54a.google.com ([2607:f8b0:4864:20::54a]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qYCMb-00EiJc-0q for linux-arm-kernel@lists.infradead.org; Mon, 21 Aug 2023 21:23:06 +0000 Received: by mail-pg1-x54a.google.com with SMTP id 41be03b00d2f7-565c824a23bso5398423a12.3 for ; Mon, 21 Aug 2023 14:23:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1692652984; x=1693257784; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=YgTaLJAmUad0YLnHfOMQe2MEne8LxCU1g5ZxaAq3g0U=; b=PIl6nC2/xM90YAB0x/YrU1gwi0CviK/tWjFaeL65SWUQbUQsgpVJRPn76978PnD4u6 bUaiGMw+W7iOfyNuZAthpf6LJK0IfuZJxGAKOM4HQxgVOzLTvOyp7yDPUmb9Ph83bDfG ndD0X9hQe7EuKGLXb4bi1CDpqCtvhSOmD/vKTKnjOYnuaZTj9q3ogcV31WaBh6QSOyx1 Nw8263cJrnqh4ffttwH7WVpUuT+SdZZkOIr7M+JIiktCM/PUS00fUySXtJrPPSXXD/BA uS14x06dGL1jh7ry9crzF+Wkj3pcTJZOipAmWYUuxHCaKUvBZdWM0hPeHvv7L7w7JzNB krxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692652984; x=1693257784; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YgTaLJAmUad0YLnHfOMQe2MEne8LxCU1g5ZxaAq3g0U=; b=A+VJlpM/mY0JT60Nd7+5m4oKVBDpYaJJcC4N7wYKAdTD66ZGceomI6JwiPzQzIE2aZ 9QEpr/VA6+bOKY5QAcACCK3Nd1oEuNTM1Asp9/JPORqNAf1/ldwz55XCJOnz6+61Ccj8 9k4a+Zft4k13aPWBhcHPsmmxES792N1S/6Cex8bvktblZo5xPzPEw4M6x4+9HfCHjmYi /+m5V2OdAOAbt7qcdDb2myXSUyV1OeeFoY1dfKCnqRnrl1krMGYsgO3DyuquwaCrvABd A2gct6u7pR2ASQsZhguE4c8XjNnaFOr8WXSQKvHeIh/ihS38JzTpXGjqlq3g29vv3HzL 9aLA== X-Gm-Message-State: AOJu0YzH3mOa/jGHpD1TGKN1vzz1SlI9MmYwytJkZm3xY1qjm5fvtdNR Wcw4DeeVV2ZWCHvKD8DVbsY4dI07VUMIgYbV+Q== X-Google-Smtp-Source: AGHT+IHMLzQuvWaAzxElJKP9Dp9OtXD637SCTtUsKnZJ0SqP6VYj3mFXGJE3BulMdkjVz/lV1VBaWwqQYtRJCXaReA== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a17:902:cec9:b0:1bc:f6d:b2f1 with SMTP id d9-20020a170902cec900b001bc0f6db2f1mr3958879plg.5.1692652983926; Mon, 21 Aug 2023 14:23:03 -0700 (PDT) Date: Mon, 21 Aug 2023 14:22:41 -0700 In-Reply-To: <20230821212243.491660-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230821212243.491660-1-jingzhangos@google.com> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog Message-ID: <20230821212243.491660-10-jingzhangos@google.com> Subject: [PATCH v9 09/11] KVM: arm64: Enable writable for ID_AA64MMFR{0, 1, 2, 3}_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Shaoqin Huang , Jing Zhang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230821_142305_295346_0253344A X-CRM114-Status: GOOD ( 10.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable writable from userspace for ID_AA64MMFR{0, 1, 2, 3}_EL1. RES0 fields and those fields not exposed by KVM are not writable. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 44d164d47756..96a1dccf1af5 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1346,9 +1346,6 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS); break; - case SYS_ID_AA64MMFR2_EL1: - val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; - break; case SYS_ID_MMFR4_EL1: val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); break; @@ -1581,6 +1578,15 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, return set_id_reg(vcpu, rd, val); } +static u64 read_sanitised_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); + + val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; + return val; +} + /* * cpufeature ID register user accessors * @@ -1936,6 +1942,10 @@ static bool access_spsr(struct kvm_vcpu *vcpu, } #define ID_AA64DFR0_EL1_RES0_MASK (GENMASK(59, 56) | GENMASK(27, 24) | GENMASK(19, 16)) +#define ID_AA64MMFR0_EL1_RES0_MASK GENMASK(55, 48) +#define ID_AA64MMFR1_EL1_RES0_MASK GENMASK(63, 60) +#define ID_AA64MMFR2_EL1_RES0_MASK GENMASK(47, 44) +#define ID_AA64MMFR3_EL1_RES0_MASK (GENMASK(59, 32) | GENMASK(27, 8)) /* * Architected system registers. @@ -2068,10 +2078,11 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_UNALLOCATED(6,7), /* CRm=7 */ - ID_SANITISED(ID_AA64MMFR0_EL1), - ID_SANITISED(ID_AA64MMFR1_EL1), - ID_SANITISED(ID_AA64MMFR2_EL1), - ID_SANITISED(ID_AA64MMFR3_EL1), + ID_SANITISED_W(ID_AA64MMFR0_EL1, ~ID_AA64MMFR0_EL1_RES0_MASK), + ID_SANITISED_W(ID_AA64MMFR1_EL1, ~ID_AA64MMFR1_EL1_RES0_MASK), + _ID_SANITISED_W(ID_AA64MMFR2_EL1, set_id_reg, read_sanitised_id_aa64mmfr2_el1, + ~(ID_AA64MMFR2_EL1_CCIDX_MASK | ID_AA64MMFR2_EL1_RES0_MASK)), + ID_SANITISED_W(ID_AA64MMFR3_EL1, ~ID_AA64MMFR3_EL1_RES0_MASK), ID_UNALLOCATED(7,4), ID_UNALLOCATED(7,5), ID_UNALLOCATED(7,6),