From patchwork Tue Aug 22 10:57:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 13360484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE233EE49A3 for ; Tue, 22 Aug 2023 10:58:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=WvXMCf+/H7mw4KIOrf8bno4Tn8CLTm3HVBMKRIZRfHg=; b=xd91VbeOWNeGvAnrRzck7rs2e5 HF4xe6+oAcIF6RFIeKKA/o5xG2FpiG0FfVl7v8sgq9udgmE/GRMjI8ZC11V6x6H1ihcVik91KyziQ tNpkzLFmUH1wU/ZdH/b/brhxratQTiF0/0zXbYJ0qVsziimjfUjgsrsV3A2Qna9sFNiY5WgJaKyrC MORG4edRJE0NXApPPVDe8DJSNnbykIJLGcfBASN6yqmajsTF1l6cEXxIUwpvoGP6xG4OHXfWteMZA DycGI0PraZx2V4oICY44kjCwlxs/Gtfw1gfSO5SW9GNIASGQCuKiR97eyEj6ZlI2SbwOFsoX/PFqT /jGg87vQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qYP5Z-00FmRm-0Z; Tue, 22 Aug 2023 10:58:21 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qYP5M-00FmKB-0B for linux-arm-kernel@lists.infradead.org; Tue, 22 Aug 2023 10:58:09 +0000 Received: by mail-pj1-x104a.google.com with SMTP id 98e67ed59e1d1-26d5094188cso4173430a91.0 for ; Tue, 22 Aug 2023 03:58:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1692701883; x=1693306683; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=klUumB39dl+OBWmiMAnKOGBWf0KJAFVzeJ+KKuR3vwQ=; b=QOdvPyWOFijq9vdM4JKXlc9Z/yC655EJi71UDoHdIoa3E1exEkCClclZJ3AnpfSNdy 2DZ07wdWinF4bADwtdysdonB6RVLAp6DvagkAG/F0pU/aytEVm0Z4NDJGVsDdGBnP5DW HBUbLjBDPewVyHjv46VGKLZSz342zyA3Ol8D0ntbfYTBh831xO+tsO6mLkF+5hr3Ze/A 2wXSFj1UY72mn5v5R6GkBTJsHH1PdZhlqGBpmToV8MySPdOkSXKZlL1eaujIjBBLB1R1 nFYWLrQjysbpQlG0Q2UM95vgzfFfCNjkiceengnYypACUamkijXuM43gQhjXt4T/OpSq oDTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692701883; x=1693306683; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=klUumB39dl+OBWmiMAnKOGBWf0KJAFVzeJ+KKuR3vwQ=; b=hc51xaHULtQOqhNta1xa+/SLd4zVq1gWlF3t2vn9x9UhP4ro2Fk/RQIIyXkICXkD7s ULMVKa0hx9Y8nJlzSooYxR1Zd3c8eyux5B/HeSuAZMuAeLEugmefVFhYoESbQ3r5uu1Z SUYzByGNQRxEUri6ieN4CTwBNRuRdN6e8RBGaTH7CUww/9Z0J6XYQ4ryYx+r2E7uQwFW GKGdF5WXmM/OUueIdDwpH/Haw7moyJ+yVZLe3SfTepZji9vgp1Q59zS4xf2/CqJueEy8 8Ct4hLHGWE50RGi7rHXG85pZDz024cjSyodzYQhWiEdUVIvnf53a63jooo73++o6bnM9 HkrA== X-Gm-Message-State: AOJu0Yw6WWXTpAVLHAWI7kVDQ6AY0ksZZtSVJaA8dXA4BDIbdRNQ4cdv pIUTp1Ei3sregHWXlV8GflI0IPHj5crG X-Google-Smtp-Source: AGHT+IGvy5fADWCBcGzxzY/Im00oXNvC+VMa0VGSdAqQOVHtJdVI4FD8dSTU2tOb1ulf37dD57VvtOXSyH1Z X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:44ad:3968:8aaa:c4fe]) (user=mshavit job=sendgmr) by 2002:a17:90a:e38f:b0:268:3469:d86e with SMTP id b15-20020a17090ae38f00b002683469d86emr1952119pjz.1.1692701883529; Tue, 22 Aug 2023 03:58:03 -0700 (PDT) Date: Tue, 22 Aug 2023 18:57:00 +0800 In-Reply-To: <20230822105738.1607365-1-mshavit@google.com> Mime-Version: 1.0 References: <20230822105738.1607365-1-mshavit@google.com> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog Message-ID: <20230822185632.RFC.v2.4.I326c62dc062aed8d901d319aa665dbe983c7904c@changeid> Subject: [RFC PATCH v2 4/9] iommu/arm-smmu-v3-sva: Allocate new ASID from installed_smmus From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: nicolinc@nvidia.com, tina.zhang@intel.com, jean-philippe@linaro.org, will@kernel.org, robin.murphy@arm.com, jgg@nvidia.com, Michael Shavit , Dawei Li , Jason Gunthorpe , Joerg Roedel , "Kirill A. Shutemov" , Lu Baolu , Mark Brown X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230822_035808_102151_71B298C5 X-CRM114-Status: GOOD ( 13.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Pick an ASID that is within the supported range of all SMMUs that the domain is installed to. Signed-off-by: Michael Shavit --- (no changes since v1) .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 23 +++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index fe88a7880ad57..92d2f8c4e90a8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -66,6 +66,20 @@ static int arm_smmu_write_ctx_desc_devices(struct arm_smmu_domain *smmu_domain, return ret; } +static u32 arm_smmu_domain_max_asid_bits(struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_master *master; + unsigned long flags; + u32 asid_bits = 16; + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, + domain_head) + asid_bits = min(asid_bits, master->smmu->asid_bits); + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + return asid_bits; +} + /* * Check if the CPU ASID is available on the SMMU side. If a private context * descriptor is using it, try to replace it. @@ -76,7 +90,6 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) int ret; u32 new_asid; struct arm_smmu_ctx_desc *cd; - struct arm_smmu_device *smmu; struct arm_smmu_domain *smmu_domain; cd = xa_load(&arm_smmu_asid_xa, asid); @@ -92,10 +105,12 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) } smmu_domain = container_of(cd, struct arm_smmu_domain, cd); - smmu = smmu_domain->smmu; - ret = xa_alloc(&arm_smmu_asid_xa, &new_asid, cd, - XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); + ret = xa_alloc( + &arm_smmu_asid_xa, &new_asid, cd, + XA_LIMIT(1, + (1 << arm_smmu_domain_max_asid_bits(smmu_domain)) - 1), + GFP_KERNEL); if (ret) return ERR_PTR(-ENOSPC); /*