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Tue, 29 Aug 2023 10:17:53 -0700 (PDT) Received: from U4.lan ([2001:9e8:b958:3410:8e0c:ed68:cd6c:7cb8]) by smtp.gmail.com with ESMTPSA id a21-20020a1709062b1500b00993cc1242d4sm6115834ejg.151.2023.08.29.10.17.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 10:17:52 -0700 (PDT) From: Alex Bee To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Lee Jones , Liam Girdwood , Mark Brown , Michael Turquette , Stephen Boyd , Vinod Koul , Kishon Vijay Abraham I Cc: Elaine Zhang , Johan Jonker , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, alsa-devel@alsa-project.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, Alex Bee Subject: [PATCH 29/31] ARM: dts: rockchip: Make usbphy the parent of SCLK_USB480M for RK312x Date: Tue, 29 Aug 2023 19:16:45 +0200 Message-ID: <20230829171647.187787-30-knaerzche@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829171647.187787-1-knaerzche@gmail.com> References: <20230829171647.187787-1-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230829_101754_722952_533986A9 X-CRM114-Status: GOOD ( 13.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Without setting the parent for SCLK_USB480M the clock will use xin24m as it's default parent. While this is generally not an issue for the usb blocks to work, but the clock driver will "think" it runs at 24 MHz. That becomes an issue for RK312x since SCLK_USB480M can be a parent for other HW blocks (users of mux_pll_src_5plls_p) but they never will choose this clock as their parent, because it runs at OSC frequency. This sets usb480m_phy as SCLK_USB480M's parent, which now runs and outputs the expected frequency of 480 MHz and the other blocks can choose SCLK_USB480M as their parent if needed. Signed-off-by: Alex Bee --- arch/arm/boot/dts/rockchip/rk312x.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk312x.dtsi b/arch/arm/boot/dts/rockchip/rk312x.dtsi index b13957d55500..19bd6448d122 100644 --- a/arch/arm/boot/dts/rockchip/rk312x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk312x.dtsi @@ -293,6 +293,8 @@ usb_host_ehci: usb@101c0000 { reg = <0x101c0000 0x20000>; interrupts = ; clocks = <&cru HCLK_HOST2>; + assigned-clocks = <&cru SCLK_USB480M>; + assigned-clock-parents = <&usb2phy>; phys = <&usb2phy_host>; phy-names = "usb"; status = "disabled"; @@ -303,6 +305,8 @@ usb_host_ohci: usb@101e0000 { reg = <0x101e0000 0x20000>; interrupts = ; clocks = <&cru HCLK_HOST2>; + assigned-clocks = <&cru SCLK_USB480M>; + assigned-clock-parents = <&usb2phy>; phys = <&usb2phy_host>; phy-names = "usb"; status = "disabled";