From patchwork Thu Aug 31 17:44:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 13371761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4ED5C83F38 for ; Thu, 31 Aug 2023 17:46:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=iOMRd2Pn/1Q+wJiD5lldZYBl2qTtPKi97V8QbFTDxO8=; b=MjegIJhPiQpVT5pcZvb0dKggZr D6lu/YKHTQKU/1UYyJ2eBtwMlgb+JjAuG3aTdn4JdLvBuTawWyLPik2m+wO4QmR+rd5KN4ysQexKu sK7s9qnVzFCvqZKnjLLCNjib6+7othForJEwObiJb1nPwGYh0R+aU5juZH907P0JkyyBGm+mnUjem g8pET4dUdFvXxRtRhbeqhA6O5rDVyJ8OIg9QXImVEm9rIu3/ZiOD+Icfvh55JXHocwlYDNhVIa5pO iVyC+sVhvtGGhYMfPFBb6FWjKnFFg4ldv8nLweRxHv8F6n7RLlSP1EyPUhJUwtQ4Rr2i9q7Mb5J8R GkyPJ1yg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qblkP-00Fen7-2I; Thu, 31 Aug 2023 17:46:25 +0000 Received: from mail-yw1-x1149.google.com ([2607:f8b0:4864:20::1149]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qblk6-00Fefx-0D for linux-arm-kernel@lists.infradead.org; Thu, 31 Aug 2023 17:46:07 +0000 Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-58fbfcb8d90so14711597b3.1 for ; Thu, 31 Aug 2023 10:46:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1693503965; x=1694108765; darn=lists.infradead.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=o+w3KBHikFTGwIimaQYuBypMhrw19N7uERmLhmvMz58=; b=DjVJ9B6kM2OP5VdMTJ47stSQH98STN6C3gLnXeKLniVFEYg0zBBX0/jgSLRdi47Voj yGTBZKpRNrH1EnW35b2asDxWPYPsl15RkyrvptLsInvyWtbtRRHnxXRMuFBqChMUUn0s tgD55alrEJ3ydPu2fzuBGxZPFXWJgFr1it9eMLLj2G2QY4IbEoi857exvR5R9ytTBybL XH5EaLmySe1BkgGgKvmL25ImybrDOHOd2iCN0yILMQE0gMq2W6vFd7BngngX4KGaq4uJ VOh03QB9gITJLyExT/zXnO+HIwdO5//SqZsbgUGoo+PX6GSs8mAvXEUZKrFNhdedYM6L jxTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693503965; x=1694108765; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=o+w3KBHikFTGwIimaQYuBypMhrw19N7uERmLhmvMz58=; b=CbvlJEc1TR++71C02l1Y1ndWs34ID/DW+zocUsoEL2kHnw5lPhDuwHIcGqpH/JJeUP GY33zHGwHVoWOcCrMgOTlThmZc5uf20/s9IAabII8KTQr0wtmd8lNuR7jN9v/qXiJxNp StaxFgV3c6WrJ3O9EvQCBI7I1Ysu+lEQd9G7cbMEnLsCD2N7COW3mslzUobbpO2kaRzC byAkK1zcN/8nhaDeXOOFmgfHcwzpzc7Z4zIZFtOJs31xFUH7lw25WUkOrIilIz3Bn9cU MWApUGq2NtnelUCp/Bta2itPNsc9zu9hUIR/5B3l7q7yOc8xrCGjKE4xrFHS53t6XZQ0 V62g== X-Gm-Message-State: AOJu0Yz+H/3+ZTGXCZbDhJZLjb29i2wvHLIvh3oBRDmCtmQjEFQkd5qY JT0NrIgp35bVTbHqEgpZadRBe8wx+9Zx X-Google-Smtp-Source: AGHT+IFAWVZV2caLtc+pnQCsFawM0vj56icg1pDwBPCBAR0uE5NsLxwemjROnxuZAPffh9wiN1C0yPtzEIKV X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:1a0a:7338:4a5a:5f83]) (user=mshavit job=sendgmr) by 2002:a81:b61f:0:b0:56f:f62b:7a11 with SMTP id u31-20020a81b61f000000b0056ff62b7a11mr2293ywh.8.1693503964944; Thu, 31 Aug 2023 10:46:04 -0700 (PDT) Date: Fri, 1 Sep 2023 01:44:33 +0800 In-Reply-To: <20230831174536.103472-1-mshavit@google.com> Mime-Version: 1.0 References: <20230831174536.103472-1-mshavit@google.com> X-Mailer: git-send-email 2.42.0.283.g2d96d420d3-goog Message-ID: <20230901014413.v7.4.I5aa89c849228794a64146cfe86df21fb71629384@changeid> Subject: [PATCH v7 4/9] iommu/arm-smmu-v3: move stall_enabled to the cd table From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, jean-philippe@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, Michael Shavit , Jason Gunthorpe , Joerg Roedel , Kevin Tian , "Kirill A. Shutemov" , Lu Baolu , Mark Brown , Yicong Yang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230831_104606_105581_685662BE X-CRM114-Status: GOOD ( 18.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A domain can be attached to multiple masters with different master->stall_enabled values. The stall bit of a CD entry should follow master->stall_enabled and has an inverse relationship with the STE.S1STALLD bit. The stall_enabled bit does not depend on any property of the domain, so move it out of the arm_smmu_domain struct. Move it to the CD table struct so that it can fully describe how CD entries should be written to it. Reviewed-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Signed-off-by: Michael Shavit --- (no changes since v5) Changes in v5: - Reword commit Changes in v2: - Use a bitfield instead of a bool for stall_enabled drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++---- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 ++- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 5bb13fadb41ad..44df7c0926802 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1114,7 +1114,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) | CTXDESC_CD_0_V; - if (smmu_domain->stall_enabled) + if (smmu_domain->cd_table.stall_enabled) val |= CTXDESC_CD_0_S; } @@ -1141,6 +1141,7 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; + cdcfg->stall_enabled = master->stall_enabled; cdcfg->s1cdmax = master->ssid_bits; max_contexts = 1 << cdcfg->s1cdmax; @@ -2119,8 +2120,6 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, if (ret) goto out_unlock; - smmu_domain->stall_enabled = master->stall_enabled; - ret = arm_smmu_alloc_cd_tables(smmu_domain, master); if (ret) goto out_free_asid; @@ -2459,7 +2458,8 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) ret = -EINVAL; goto out_unlock; } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && - smmu_domain->stall_enabled != master->stall_enabled) { + smmu_domain->cd_table.stall_enabled != + master->stall_enabled) { ret = -EINVAL; goto out_unlock; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 5f0e7468db5f3..007758df57610 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -598,6 +598,8 @@ struct arm_smmu_ctx_desc_cfg { u8 s1fmt; /* log2 of the maximum number of CDs supported by this table */ u8 s1cdmax; + /* Whether CD entries in this table have the stall bit set. */ + u8 stall_enabled:1; }; struct arm_smmu_s2_cfg { @@ -715,7 +717,6 @@ struct arm_smmu_domain { struct mutex init_mutex; /* Protects smmu pointer */ struct io_pgtable_ops *pgtbl_ops; - bool stall_enabled; atomic_t nr_ats_masters; enum arm_smmu_domain_stage stage;