Message ID | 20230905082916.18852-5-c.tenruh@phytec.de (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Update of phyBOARD-Pollux-i.MX8MP | expand |
On Tue, Sep 5, 2023 at 5:29 AM Cem Tenruh <c.tenruh@phytec.de> wrote: > > From: Teresa Remmet <t.remmet@phytec.de> > > Add UART2 for RS232/RS485 support. > > Signed-off-by: Teresa Remmet <t.remmet@phytec.de> > (Updated the node by not setting the reserved bits(BIT 0 and BIT 3) > and enabled internal pullup for RX and TX.) > Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index f2620dea19ed..0b867f348816 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -178,6 +178,16 @@ &usb_dwc3_1 { status = "okay"; }; +/* RS232/RS485 */ +&uart2 { + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + /* SD-Card */ &usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; @@ -299,6 +309,15 @@ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 >; }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140 + MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140 + >; + }; + pinctrl_usdhc2_pins: usdhc2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4