From patchwork Tue Sep 5 10:47:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 13374425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC52CC83F33 for ; Tue, 5 Sep 2023 10:48:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2IOLoxzcHqfZ6V7oW9n2IgPjzV/BGQhD/zNCtUh4mI0=; b=fpr9UpM3Lha1uG An4jGWsMnpS0c8g3rxha6TjKttvwdBWZQLlRJXYpONVzQ3Pffy/GfkWkWHTqkJjLWaLrU5AbBZfxu N72aA6ftpEipBo1cYgoz/JoazvAmEg2EENOAVwKRVTiM3UJnfT+Lc03kyKxp0acW+DHbMPAg8G6Os 32oKhUsKzVcE9kxzBxaZrHOOI5wd/q3mxudWtq3MFrK7de4dn2DlYCpXFcWdOcQzF3E2/abayBhzE Gch0SWr7lVdEfHD7495swJXV8Uxeg9HrT0MpfxiB7FuRi4YMh0BuBA7HuWOwVZoZ2HhUG4kYDjtZu ++Fw9BCqPR2Dme4jPZ3g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qdTat-005qz7-2O; Tue, 05 Sep 2023 10:47:39 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qdTar-005qxp-12 for linux-arm-kernel@lists.infradead.org; Tue, 05 Sep 2023 10:47:38 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 54925B811E1; Tue, 5 Sep 2023 10:47:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1AA8C433A9; Tue, 5 Sep 2023 10:47:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1693910855; bh=be3LTeFm799ZIVXUkbKCDmqLg5EZsxWtrrfYzGafTQ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kn2eZZwyL2WrmDC9u1LV85D4PdFEhtw9KkxYls2VcOJ2Yo5YjFuIJlGgulxVuvPra wUc6CkhPD1ZV7DFJe348R2JAET0zkHfPX6h3CS/rx2IC54DEuvPd1Q5wHPFgF3rNo9 hC7IQr88u5L6Cz5LXpYaTnvBueqMQTWjTFPrtEEElSUmNeTdF8cP72MVF8ddZoPBo4 mvYv8Yor76j11jo4Jb13UrqWUyHpfvFSX3Ew5YJu/ryRtvi9X9z+SXOCJfzDrLFfvY 98WKpVK0lpoX6BgwGDci2DWb2UkybEtadDt8A21tDQnvYxmzyjGQeAFTqv20f0fwe1 whP6SGZ3DfxDA== From: Lorenzo Pieralisi To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , Robin Murphy , Mark Rutland , Marc Zyngier , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Rob Herring , Fang Xiang Subject: [PATCH 2/2] irqchip/gic-v3: Enable non-coherent redistributors/ITSes probing Date: Tue, 5 Sep 2023 12:47:21 +0200 Message-Id: <20230905104721.52199-3-lpieralisi@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905104721.52199-1-lpieralisi@kernel.org> References: <20230905104721.52199-1-lpieralisi@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230905_034737_660735_2ED4FBDF X-CRM114-Status: GOOD ( 20.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The GIC architecture specification defines a set of registers for redistributors and ITSes that control the sharebility and cacheability attributes of redistributors/ITSes initiator ports on the interconnect (GICR_[V]PROPBASER, GICR_[V]PENDBASER, GITS_BASER). Architecturally the GIC provides a means to drive shareability and cacheability attributes signals and related IWB/OWB/ISH barriers but it is not mandatory for designs to wire up the corresponding interconnect signals that control the cacheability/shareability of transactions. Redistributors and ITSes interconnect ports can be connected to non-coherent interconnects that are not able to manage the shareability/cacheability attributes; this implicitly makes the redistributors and ITSes non-coherent observers. So far, the GIC driver on probe executes a write to "probe" for the redistributors and ITSes registers shareability bitfields by writing a value (ie InnerShareable - the shareability domain the CPUs are in) and check it back to detect whether the value sticks or not; this hinges on a GIC programming model behaviour that predates the current specifications, that just define shareability bits as writeable but do not guarantee that writing certain shareability values enable the expected behaviour for the redistributors/ITSes memory interconnect ports. To enable non-coherent GIC designs, introduce the "dma-noncoherent" device tree property to allow firmware to describe redistributors and ITSes as non-coherent observers on the memory interconnect and use the property to force the shareability attributes to be programmed into the redistributors and ITSes registers. Signed-off-by: Lorenzo Pieralisi Cc: Robin Murphy Cc: Mark Rutland Cc: Marc Zyngier Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index e0c2b10d154d..758ea3092305 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -5056,7 +5056,8 @@ static int __init its_compute_its_list_map(struct resource *res, } static int __init its_probe_one(struct resource *res, - struct fwnode_handle *handle, int numa_node) + struct fwnode_handle *handle, int numa_node, + bool non_coherent) { struct its_node *its; void __iomem *its_base; @@ -5148,7 +5149,7 @@ static int __init its_probe_one(struct resource *res, gits_write_cbaser(baser, its->base + GITS_CBASER); tmp = gits_read_cbaser(its->base + GITS_CBASER); - if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) + if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE || non_coherent) tmp &= ~GITS_CBASER_SHAREABILITY_MASK; if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { @@ -5356,11 +5357,19 @@ static const struct of_device_id its_device_id[] = { {}, }; +static void of_check_rdists_coherent(struct device_node *node) +{ + if (of_property_read_bool(node, "dma-noncoherent")) + gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE; +} + static int __init its_of_probe(struct device_node *node) { struct device_node *np; struct resource res; + of_check_rdists_coherent(node); + /* * Make sure *all* the ITS are reset before we probe any, as * they may be sharing memory. If any of the ITS fails to @@ -5396,7 +5405,8 @@ static int __init its_of_probe(struct device_node *node) continue; } - its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); + its_probe_one(&res, &np->fwnode, of_node_to_nid(np), + of_property_read_bool(np, "dma-noncoherent")); } return 0; } @@ -5533,7 +5543,8 @@ static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header, } err = its_probe_one(&res, dom_handle, - acpi_get_its_numa_node(its_entry->translation_id)); + acpi_get_its_numa_node(its_entry->translation_id), + false); if (!err) return 0;