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bh=hl0F/+pZ+bwJxmBvTp5xxZywrriDZvOWTyU7VhZJKMM=; b=iIcfqCMO8C+Crov7SAXGEERfJT3CAxyluIQmQILXDFQNYU1awTl/cE2JbDYBggmY nPuJstlyxipCJJY/8U6HeviRpPgcDTKq22h57583BZmVAuzNRgeuYpuK/9AO0OHh tZjo906elpMBwMCZze1KF/+Xdj+2ragC72yAgy3/bBU=; X-AuditID: ac14000a-6e25770000001e37-dc-64f84fbcf1b8 Received: from idefix.phytec.de (Unknown_Domain [172.25.0.20]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 32.5D.07735.CBF48F46; Wed, 6 Sep 2023 12:09:00 +0200 (CEST) Received: from llp-ausleih01.fritz.box ([172.25.39.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2023090612090029-11065 ; Wed, 6 Sep 2023 12:09:00 +0200 From: Cem Tenruh To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Cc: linux-arm-kernel@lists.infradead.org, upstream@lists.phytec.de Subject: [PATCH v4 5/5] arm64: dts: imx8mp-phyboard-pollux: Add support for RS232/RS485 Date: Wed, 6 Sep 2023 12:08:57 +0200 Message-Id: <20230906100857.7916-6-c.tenruh@phytec.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230906100857.7916-1-c.tenruh@phytec.de> References: <20230906100857.7916-1-c.tenruh@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 06.09.2023 12:09:00, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 06.09.2023 12:09:00 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCLMWRmVeSWpSXmKPExsWyRpJBRHeP/48UgyvLVC3W7D3HZPHwqr/F qqk7WSz6Xjxkttj0+BqrRdevlcwWrXuPsFv83b6JxeLFFnGL7nfqDlweO2fdZffYtKqTzePO tT1sHpuX1Hv0d7ewemx8t4PJo/+vQQB7FJdNSmpOZllqkb5dAlfGii972Au281fM3T6LrYGx lbeLkZNDQsBE4t+2m8wgtpDANkaJ5slyXYxcQPZFRok1mw6CJdgEVCXmHZsIZosIHGKSWHkl DsRmFnCS+NjwlQXEFhYIlzh85SEbiM0ioCJx79F7sHpeATOJbX96GSGWyUvsP3gWLM4pYC5x eNsKNojFZhIn5/xmhagXlDg58wkLyBESAlcYJT6f28YM0SwkcXoxRDOzgLbEsoWvmScwCsxC 0jMLSWoBI9MqRqHczOTs1KLMbL2CjMqS1GS9lNRNjKCQF2Hg2sHYN8fjECMTB+MhRgkOZiUR 3nfy31KEeFMSK6tSi/Lji0pzUosPMUpzsCiJ897vYUoUEkhPLEnNTk0tSC2CyTJxcEo1MDKU aIYtaZ/05XS5lWqWSM+uLss2wdsTrixdmfnhr9BNjZUPo/ZX1W4tP/spM0aT3WznzYt+Bpsv bF7XVrvisNSbCUxCxhJrizYI3S8MvTAt3HG+znW5R6E7tBIPxfe8qmKVvaGxZ4FtzMXmxcd1 tnX/PdYWsej8NW3Jl2dYantl5px6ec1WuUCJpTgj0VCLuag4EQBt6T8oZwIAAA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230906_110911_498801_AE8CA929 X-CRM114-Status: GOOD ( 11.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Teresa Remmet Add UART2 for RS232/RS485 support. Signed-off-by: Teresa Remmet (Updated the node by not setting the reserved bits(BIT 0 and BIT 3) and enabled internal pullup for RX and TX.) Signed-off-by: Yashwanth Varakala Signed-off-by: Cem Tenruh Reviewed-by: Fabio Estevam --- Changes in v4: - Added my missing "signed-off-by" Changes in v3: - No changes Changes in v2: - Edited commit message - Added comment to UART2 node --- .../freescale/imx8mp-phyboard-pollux-rdk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 562d4fee2011..c8640cac3edc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -177,6 +177,16 @@ &usb_dwc3_1 { status = "okay"; }; +/* RS232/RS485 */ +&uart2 { + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + /* SD-Card */ &usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; @@ -298,6 +308,15 @@ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 >; }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140 + MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140 + >; + }; + pinctrl_usdhc2_pins: usdhc2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4