| Message ID | 20230912045157.177966-35-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK | expand |
Hi Claudiu, On Tue, Sep 12, 2023 at 6:53 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add initial device tree for RZ SMARC Carrier-II. At the moment it > contains only serial interface (and its pins definition). > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi > @@ -0,0 +1,28 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ SMARC Carrier-II Board. > + * > + * Copyright (C) 2023 Renesas Electronics Corp. > + */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> > + > +/ { > + aliases { > + serial0 = &scif0; > + }; > +}; > + > +&pinctrl { > + scif0_pins: scif0 { > + pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* TXD */ RXD > + <RZG2L_PORT_PINMUX(6, 4, 1)>; /* RXD */ TXD > + }; > +}; The rest LGTM. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi new file mode 100644 index 000000000000..197b529d4334 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ SMARC Carrier-II Board. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/ { + aliases { + serial0 = &scif0; + }; +}; + +&pinctrl { + scif0_pins: scif0 { + pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* TXD */ + <RZG2L_PORT_PINMUX(6, 4, 1)>; /* RXD */ + }; +}; + +&scif0 { + pinctrl-names = "default"; + pinctrl-0 = <&scif0_pins>; + status = "okay"; +};