From patchwork Tue Sep 12 12:11:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13381561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 811D3CA0ECA for ; Tue, 12 Sep 2023 12:12:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=dtqH0d/pvpB/XPXbiuz6T7Xg6FwPHYKost0PR5wXSEA=; b=qUTM4bwod98YB4 T4dJaJehV27zaKc6vhs0BGeiqArF+w4eCt7L9tiCGdM3OA9fa48pQhC0GHDG7i5iXK3PETdgvPZZL iqWOY0q+qYaD/rBn80KofNrRqh3fQgR3xuphhKtchIXXktZBLAPrQbKkc1UF7838mC5y8WitThkD0 Betn32Qy4a4z1R2/jid17gGmaCxgJX4gggfQ8uoWnt5oijUdteB59W0tfoyfL7CudelWs0yrCpvxf O1MFQNnBYI3eSXDDyfML/2E4F/Oi6c94VeIn4H4T4PVsQuVd8g7rmw++f1DqmSo2GeEaJPHdGzK2N uGT9q2d5+c3+AcvuwaWw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg2Ey-003IbW-1r; Tue, 12 Sep 2023 12:11:36 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qg2Ev-003IaF-25 for linux-arm-kernel@lists.infradead.org; Tue, 12 Sep 2023 12:11:35 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id EA4A4CE1B8E; Tue, 12 Sep 2023 12:11:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C41B7C433C7; Tue, 12 Sep 2023 12:11:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1694520686; bh=KXNNit1NR0Sy8mgpeMe5utffy8Ysa2Z5Lh2pnEXXbtY=; h=From:To:Cc:Subject:Date:From; b=MqOlKaLiuoyjAdBLO5SRg2YsMzBaQeoMfgxh6uUAYTQ7qzik7rNC1Xid7haASVvN7 9VGIVRKdO1vxWv42KfVk4tfuJyOs4O5VkYNKUDe+MNQGPHvRpPPqsUTvXLdLyJRYEW WyyaEkxQgvItBsK5kxhkExvlrUA33dynP1vnbgsPBtPB+hXiD3mD59UrJCNcZ4oCrf W2GU6ew3DOHMc/BhslpTUMxb6f4sELYcxfZRoqQhDU9seEeDeFyMiBN1qnar4B71Av lNEZmsLaNWpKVlY+vkGsWhvgBDorrd03Z3A1UEi7ZaGPCo13nN3Ab8dz29aiIp1shz zpMi8CUDGcwxQ== Received: (nullmailer pid 380681 invoked by uid 1000); Tue, 12 Sep 2023 12:11:24 -0000 From: Rob Herring To: Catalin Marinas , Will Deacon Cc: James Morse , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] arm64: Add Cortex-A520 CPU part definition Date: Tue, 12 Sep 2023 07:11:14 -0500 Message-Id: <20230912121120.380420-1-robh@kernel.org> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230912_051133_910187_50E61701 X-CRM114-Status: GOOD ( 10.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the CPU Part number for the new Arm design. Cc: stable@vger.kernel.org Signed-off-by: Rob Herring --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 5f6f84837a49..74d00feb62f0 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -79,6 +79,7 @@ #define ARM_CPU_PART_CORTEX_A78AE 0xD42 #define ARM_CPU_PART_CORTEX_X1 0xD44 #define ARM_CPU_PART_CORTEX_A510 0xD46 +#define ARM_CPU_PART_CORTEX_A520 0xD80 #define ARM_CPU_PART_CORTEX_A710 0xD47 #define ARM_CPU_PART_CORTEX_A715 0xD4D #define ARM_CPU_PART_CORTEX_X2 0xD48 @@ -148,6 +149,7 @@ #define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE) #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) +#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)