From patchwork Tue Sep 19 09:51:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 13391082 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77508CD54A9 for ; Tue, 19 Sep 2023 09:52:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=K4VkTQRQnl7d1lybcLglPAcxER0AYk6P5MUr9dIjTeg=; b=hE0fIGXrZfE54E oqpOxIWHxtrTt3sAyyqABeieLHW5/Prs2QWfkJ6MW1OvwWtsvoX9WMClgcu9MqFzZrSN4LXxPYF49 p3yTkLgLzpB9qQcllBhdxpFT8i8QQMHFb9yq6ZXbQcvsI8wcrB4of6vnhsTlTeWioRu8oJpJAuEMM PSszeFLsdnDfSDClyetsozG8b+e7DuELEjbHyUQD9K/sPBf9JUWWpF2Uu+vfKUyJaJeHhClWJtzVC gfHvyK99vERLfDwzXUudZTyqbPSbU+krBKg4mbXqoMY3AO7ja2FLIAtdJa7gPmFl7AtLKm06cVOJ1 ztb/bFo1JTnnNY3HblRg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qiXP2-00HYI6-27; Tue, 19 Sep 2023 09:52:20 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qiXOz-00HYHH-0j for linux-arm-kernel@lists.infradead.org; Tue, 19 Sep 2023 09:52:18 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D19891FB; Tue, 19 Sep 2023 02:52:53 -0700 (PDT) Received: from e127643.broadband (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id ED23F3F67D; Tue, 19 Sep 2023 02:52:14 -0700 (PDT) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: James Clark , Catalin Marinas , Will Deacon , Jonathan Corbet , Mark Rutland , Marc Zyngier , Zaid Al-Bassam , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] Documentation: arm64: Document the PMU event counting threshold feature Date: Tue, 19 Sep 2023 10:51:29 +0100 Message-Id: <20230919095137.360963-3-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230919095137.360963-1-james.clark@arm.com> References: <20230919095137.360963-1-james.clark@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230919_025217_314303_23D6C240 X-CRM114-Status: GOOD ( 13.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add documentation for the two new Perf event open parameters and the threshold_max capability file. Signed-off-by: James Clark --- Documentation/arch/arm64/perf.rst | 58 +++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/Documentation/arch/arm64/perf.rst b/Documentation/arch/arm64/perf.rst index 1f87b57c2332..122a12607f37 100644 --- a/Documentation/arch/arm64/perf.rst +++ b/Documentation/arch/arm64/perf.rst @@ -164,3 +164,61 @@ and should be used to mask the upper bits as needed. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c .. _tools/lib/perf/tests/test-evsel.c: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.c + +Event Counting Threshold +========================================== + +Overview +-------- + +FEAT_PMUv3_TH (Armv8.8) permits a PMU counter to increment only on +events whose count meets a specified threshold condition. For example if +threshold_control is set to 5 ('Greater than or equal, count'), and +the threshold is set to 2, then the PMU counter will now only increment +by 1 when an event would have previously incremented the PMU counter by +2 or more on a single processor cycle. + +To increment by the value of the event instead of 1, use the non 'count' +comparisons, in this case 4 ('Greater than or equal'). Each comparison +has a count and non count version, where the 'count' version always +increments the PMU counter by 1 instead of the value of the event. + +How-to +------ + +The threshold and threshold control values can be provided per event: + +.. code-block:: sh + + perf stat -e stall_slot/threshold=2,threshold_control=5/ \ + -e dtlb_walk/threshold=10,threshold_control=4/ + +And the following control values are supported: + +.. code-block:: + + 0: Not-equal + 1: Not-equal, count + 2: Equals + 3: Equals, count + 4: Greater-than-or-equal + 5: Greater-than-or-equal, count + 6: Less-than + 7: Less-than, count + +The maximum supported threshold value can be read from the caps of each +PMU, for example: + +.. code-block:: sh + + cat /sys/bus/event_source/devices/armv8_pmuv3/caps/threshold_max + + 0x000000ff + +If a value higher than this is given, then it will be silently clamped +to the maximum. The highest possible maximum is 4095, as the config +field for threshold is limited to 12 bits, and the Perf tool will refuse +to parse higher values. + +If the PMU doesn't support FEAT_PMUv3_TH, then threshold_max will read +0, and both threshold and threshold_control will be silently ignored.