Message ID | 20230920065459.12738-6-quic_tengfan@quicinc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Wed, 20 Sep 2023 06:56:10 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 19 Sep 2023 23:56:01 -0700 From: Tengfei Fan <quic_tengfan@quicinc.com> To: <agross@kernel.org>, <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <tglx@linutronix.de>, <maz@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>, <catalin.marinas@arm.com>, <will@kernel.org> CC: <geert+renesas@glider.be>, <arnd@arndb.de>, <neil.armstrong@linaro.org>, <nfraprado@collabora.com>, <rafal@milecki.pl>, <peng.fan@nxp.com>, <linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <quic_tsoni@quicinc.com>, <quic_shashim@quicinc.com>, <quic_kaushalk@quicinc.com>, <quic_tdas@quicinc.com>, <quic_tingweiz@quicinc.com>, <quic_aiquny@quicinc.com>, <quic_ajipan@quicinc.com>, <kernel@quicinc.com>, Tengfei Fan <quic_tengfan@quicinc.com> Subject: [PATCH v3 5/5] arm64: defconfig: enable clock controller and pinctrl for SM4450 Date: Wed, 20 Sep 2023 14:54:59 +0800 Message-ID: <20230920065459.12738-6-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230920065459.12738-1-quic_tengfan@quicinc.com> References: <20230920065459.12738-1-quic_tengfan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: BBoMmDX8I1JBsjmVZIpfWaXpuDBCblBS X-Proofpoint-ORIG-GUID: BBoMmDX8I1JBsjmVZIpfWaXpuDBCblBS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-20_02,2023-09-19_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 suspectscore=0 mlxlogscore=660 mlxscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309200055 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230919_235627_902012_3C2A995F X-CRM114-Status: GOOD ( 15.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: <linux-arm-kernel.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-arm-kernel>, <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/> List-Post: <mailto:linux-arm-kernel@lists.infradead.org> List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>, <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org |
Series |
soc: qcom: Add uart console support for SM4450
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diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 77c63c24b3a0..5bc9e9e94cf6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -598,6 +598,7 @@ CONFIG_PINCTRL_SC8280XP=y CONFIG_PINCTRL_SDM660=y CONFIG_PINCTRL_SDM670=y CONFIG_PINCTRL_SDM845=y +CONFIG_PINCTRL_SM4450=y CONFIG_PINCTRL_SM6115=y CONFIG_PINCTRL_SM6125=y CONFIG_PINCTRL_SM6350=y @@ -1242,6 +1243,7 @@ CONFIG_SM_DISPCC_6115=m CONFIG_SM_DISPCC_8250=y CONFIG_SM_DISPCC_8450=m CONFIG_SM_DISPCC_8550=m +CONFIG_SM_GCC_4450=y CONFIG_SM_GCC_6115=y CONFIG_SM_GCC_8350=y CONFIG_SM_GCC_8450=y
Enable global clock controller and pinctrl for support the Qualcomm SM4450 platform to boot to UART console. The serial engine depends on some global clock controller and pinctrl, but as the serial console driver is only available as built-in, so the global clock controller and pinctrl also needs be built-in for the UART device to probe and register the console. Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+)