@@ -354,7 +354,7 @@ pins1 {
ethernet0_rgmii_pins_d: rgmii-3 {
pins1 {
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+ pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
@@ -384,8 +384,7 @@ pins3 {
ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 {
pins1 {
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
On the phyCORE-STM32MP15 the 125MHz clock for the ethernet phy must be provided on the ETH_RGMII_GTX_CLK. ETH_RGMII_CLK125 is unused though, so remove the latter pin and add the former. ethernet0_rgmii_pins_d and ethernet0_rgmii_sleep_pins_d are used by the phyCORE-STM32MP15 board only, so we can do this change in the generic pinctrl file without breaking other boards. Fixes: 303f3fe1d88f ("ARM: dts: stm32: Add alternate pinmux for ethernet for stm32mp15") Cc: stable@vger.kernel.org Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)