From patchwork Wed Sep 27 04:18:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13399892 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14E30E7E62A for ; Wed, 27 Sep 2023 04:19:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=cAILfbkaHaiCzGZc8NVlB+mPz1Y5u6gUu/bPodTmnwo=; b=e3fUsgrj1Vf0Yb B6xDJuD70yQrFf7Bzbz4ywRtNA4gObrc/I+wJE8I3Q+yzvCyffVWeDPH8eoa8LdWHTFRYtqbcd4KL OffdiUt+aq6OQc7kcpD2Icpjl2na6Km4ix0ddwWsg+GueVgaPGBCsbEQ5GUgb2aNy0AzvMORQyKGv NObGbQ8NDqNxkFWzQAg53/dc+rdO9eMr4yydR7jxIUmZ7o55MOzSfTXiRJktZnmGO30kKkt4LVLKU RQqQqtcyP0OPYe3f8CbIkhoGM1CJEL4vZuyVZN5xPRIVcG5T1Gytx7wMjG4bZGKGchwgldIbmj1ca Al49XLEntqU5HSXf32Dw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qlM10-00HVyY-0i; Wed, 27 Sep 2023 04:19:10 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qlM0w-00HVx5-0u for linux-arm-kernel@lists.infradead.org; Wed, 27 Sep 2023 04:19:07 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 38R4Ipcg064494; Tue, 26 Sep 2023 23:18:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1695788331; bh=b+v0kXcbL/x8WGX8epMNqGlxkmAzB2Gr+GgRtU6z/Ss=; h=From:To:CC:Subject:Date; b=S9GWVUfNGSqeP/G8Qrr/cqRFpqfWiEQzfZnOBvNqahHcM0KzNmshQ/YkGq0sH7hWp 2CbsAodbidGI1QRDp0dVfhe4kW51h9vEYQGaV3CxD2BQ/pAmCxlhInEOJLX/031Y4D /HJ0/5Mu3DpNTEU34336ORjh9LjvYufc4ws4rQDA= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 38R4IoWx003148 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 26 Sep 2023 23:18:51 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 26 Sep 2023 23:18:50 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 26 Sep 2023 23:18:50 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 38R4IkJp057625; Tue, 26 Sep 2023 23:18:46 -0500 From: Siddharth Vadapalli To: , , , CC: , , , , , , , Subject: [PATCH v3] PCI: keystone: Fix race condition when initializing PHYs Date: Wed, 27 Sep 2023 09:48:45 +0530 Message-ID: <20230927041845.1222080-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230926_211906_406928_8C2E0599 X-CRM114-Status: GOOD ( 16.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PCI driver invokes the PHY APIs using the ks_pcie_enable_phy() function. The PHY in this case is the Serdes. It is possible that the PCI instance is configured for 2 lane operation across two different Serdes instances, using 1 lane of each Serdes. In such a configuration, if the reference clock for one Serdes is provided by the other Serdes, it results in a race condition. After the Serdes providing the reference clock is initialized by the PCI driver by invoking its PHY APIs, it is not guaranteed that this Serdes remains powered on long enough for the PHY APIs based initialization of the dependent Serdes. In such cases, the PLL of the dependent Serdes fails to lock due to the absence of the reference clock from the former Serdes which has been powered off by the PM Core. Fix this by obtaining reference to the PHYs before invoking the PHY initialization APIs and releasing reference after the initialization is complete. Fixes: 49229238ab47 ("PCI: keystone: Cleanup PHY handling") Signed-off-by: Siddharth Vadapalli Acked-by: Ravi Gunasekaran --- NOTE: This patch is based on linux-next tagged next-20230927. v2: https://lore.kernel.org/r/20230926063638.1005124-1-s-vadapalli@ti.com/ Changes since v2: - Implement suggestion by Ilpo Järvinen moving the phy_pm_runtime_put_sync() For-Loop section before the return value of ks_pcie_enable_phy(ks_pcie) is checked, thereby preventing duplication of the For-Loop. - Rebase patch on next-20230927. v1: https://lore.kernel.org/r/20230926054200.963803-1-s-vadapalli@ti.com/ Changes since v1: - Add code to release reference(s) to the phy(s) when ks_pcie_enable_phy(ks_pcie) fails. Regards, Siddharth. drivers/pci/controller/dwc/pci-keystone.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 49aea6ce3e87..0ec6720cc2df 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -1218,7 +1218,16 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_link; } + /* Obtain reference(s) to the phy(s) */ + for (i = 0; i < num_lanes; i++) + phy_pm_runtime_get_sync(ks_pcie->phy[i]); + ret = ks_pcie_enable_phy(ks_pcie); + + /* Release reference(s) to the phy(s) */ + for (i = 0; i < num_lanes; i++) + phy_pm_runtime_put_sync(ks_pcie->phy[i]); + if (ret) { dev_err(dev, "failed to enable phy\n"); goto err_link;