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Tue, 3 Oct 2023 01:22:31 -0500 From: Jay Buddhabhatti To: , , CC: , , , Jay Buddhabhatti Subject: [PATCH 2/2] drivers: clk: zynqmp: update divider round rate logic Date: Mon, 2 Oct 2023 23:21:53 -0700 Message-ID: <20231003062153.12215-3-jay.buddhabhatti@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231003062153.12215-1-jay.buddhabhatti@amd.com> References: <20231003062153.12215-1-jay.buddhabhatti@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CF:EE_|SA1PR12MB7271:EE_ X-MS-Office365-Filtering-Correlation-Id: 95873bb7-6ea9-463a-a3ee-08dbc3d9218d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Yr0NCl9SVktay39afOXzB7+hn/+GLu6oD+UjGSWY1sw5j7wjkECRnTM38qmKiX3s7zNSISbdKx8ZNc4loxD0pWBSlgabDd9JJOYRVwnCAOYYe2uCv/5oJBmXQ//g5RLAU8LwRgkeqTsigTL9ZnBKessaOor6eXDEKR3CWZ1o+p6jxn+xC/HlVAjPdCsDBQVfm+X+Uef0YMnNe1V7uWy6wqzOv3pYBU+GRIYpfLdp37opXsZAO3pPlpWVNPGevd8gpBk3PhnvFw4zjJ6+xjbX9DK0JNaDZDH1xp33X55rlL84gJCfELzTGkelcWbWCoVHtAL6UPZX4IgwPxEMGLR8UCUQmEuSKu0oJVv2XMYv1K8G7wny+IuCuXKBNUrAQjWY649/sGM/C7myYsuvgrGc2Z2XBwARcWIb++8LCoo9l7cbuW91QWT7h/cl+Lc+tlwJJ6jEgN7vl3U5MEMaiwtxCD41j/SXVvgq60PoV0rkvV6CgxDtNPCx1DSKPNthFx0m8h/IvwxYGPV0e6SzD2S4fSyeRZcMwh3+mlF0PxGa+8IV/rhlZXljJJaGZWEL1Z9Bltitps3p9drJjLScj2rO2+RQlxFADxhMbaZCvFJWce2u7x0cryih1BjUzqqd1kcLiQy7B88x/vetybeAvkEQSPSM3v0yAG1RsteQDg+R3RiXWpDsNkUXOLT4PBtXJAPvnKkSF0KkFsJ8EEckzKQKQxoiMCW0YWk6ayTsj5eQMENYuRHVZMubRG83Idi/tWG0udbIlurYRxwodF6zocrBtg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(396003)(346002)(39860400002)(376002)(230922051799003)(1800799009)(451199024)(64100799003)(186009)(82310400011)(36840700001)(46966006)(40470700004)(110136005)(4326008)(70586007)(41300700001)(70206006)(44832011)(8676002)(8936002)(478600001)(54906003)(426003)(26005)(336012)(1076003)(2616005)(83380400001)(2906002)(47076005)(6666004)(36860700001)(81166007)(356005)(5660300002)(6636002)(86362001)(316002)(82740400003)(36756003)(40480700001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Oct 2023 06:22:34.0369 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95873bb7-6ea9-463a-a3ee-08dbc3d9218d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7271 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231002_232245_800279_B8DE142B X-CRM114-Status: GOOD ( 14.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently zynqmp divider round rate is considering single parent and calculating rate and parent rate accordingly. But if divider clock flag is set to SET_RATE_PARENT then its not trying to traverse through all parent rate and not selecting best parent rate from that. So use common divider_round_rate() which is traversing through all clock parents and its rate and calculating proper parent rate. Signed-off-by: Jay Buddhabhatti --- drivers/clk/zynqmp/divider.c | 70 ++++++------------------------------ 1 file changed, 10 insertions(+), 60 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 33a3b2a22659..a42c183d7e5d 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -110,52 +110,6 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, return DIV_ROUND_UP_ULL(parent_rate, value); } -static void zynqmp_get_divider2_val(struct clk_hw *hw, - unsigned long rate, - struct zynqmp_clk_divider *divider, - u32 *bestdiv) -{ - int div1; - int div2; - long error = LONG_MAX; - unsigned long div1_prate; - struct clk_hw *div1_parent_hw; - struct zynqmp_clk_divider *pdivider; - struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw); - - if (!div2_parent_hw) - return; - - pdivider = to_zynqmp_clk_divider(div2_parent_hw); - if (!pdivider) - return; - - div1_parent_hw = clk_hw_get_parent(div2_parent_hw); - if (!div1_parent_hw) - return; - - div1_prate = clk_hw_get_rate(div1_parent_hw); - *bestdiv = 1; - for (div1 = 1; div1 <= pdivider->max_div;) { - for (div2 = 1; div2 <= divider->max_div;) { - long new_error = ((div1_prate / div1) / div2) - rate; - - if (abs(new_error) < abs(error)) { - *bestdiv = div2; - error = new_error; - } - if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) - div2 = div2 << 1; - else - div2++; - } - if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO) - div1 = div1 << 1; - else - div1++; - } -} - /** * zynqmp_clk_divider_round_rate() - Round rate of divider clock * @hw: handle between common and hardware-specific interfaces @@ -174,6 +128,8 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, u32 div_type = divider->div_type; u32 bestdiv; int ret; + u8 width = 0; + u16 max; /* if read only, just return current value */ if (divider->flags & CLK_DIVIDER_READ_ONLY) { @@ -193,23 +149,17 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); } - bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags); - - /* - * In case of two divisors, compute best divider values and return - * divider2 value based on compute value. div1 will be automatically - * set to optimum based on required total divider value. - */ - if (div_type == TYPE_DIV2 && - (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { - zynqmp_get_divider2_val(hw, rate, divider, &bestdiv); + max = divider->max_div; + while (max != 0) { + if ((max & 1) == 1) + width++; + max = max >> 1; } - if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) - bestdiv = rate % *prate ? 1 : bestdiv; + rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags); - bestdiv = min_t(u32, bestdiv, divider->max_div); - *prate = rate * bestdiv; + if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate)) + *prate = rate; return rate; }