| Message ID | 20231009084957.18536-2-jian.yang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCI: mediatek-gen3: Support controlling power supplies | expand |
Il 09/10/23 10:49, Jian Yang ha scritto: > From: "jian.yang" <jian.yang@mediatek.com> > > Add new properties to support control power supplies and reset pin of > a downstream component. > > Signed-off-by: jian.yang <jian.yang@mediatek.com> > --- > .../bindings/pci/mediatek-pcie-gen3.yaml | 30 +++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > index 7e8c7a2a5f9b..eb4ad98549d1 100644 > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > @@ -84,6 +84,26 @@ properties: > items: > enum: [ phy, mac ] > > + pcie1v8-supply: There are another two controllers having such regulators and they all have the same name for those supplies; Can you please change the names to be consistent with the other controllers? vpcie1v8 vpcie3v3 vpcie12v Regards, Angelo
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 7e8c7a2a5f9b..eb4ad98549d1 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -84,6 +84,26 @@ properties: items: enum: [ phy, mac ] + pcie1v8-supply: + description: + The regulator phandle that provides 1.8V power from root port to a + downstream component. + + pcie3v3-supply: + description: + The regulator phandle that provides 3.3V power from root port to a + downstream component. + + pcie12v-supply: + description: + The regulator phandle that provides 12V power from root port to a + downstream component. + + dsc-reset-gpios: + description: + The extra reset pin other than PERST# required by a downstream component. + maxItems: 1 + clocks: minItems: 4 maxItems: 6 @@ -238,5 +258,15 @@ examples: #interrupt-cells = <1>; interrupt-controller; }; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + pcie-3v3-supply = <&pcie3v3_regulator>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; };