From patchwork Tue Oct 10 06:29:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao X-Patchwork-Id: 13414833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A86DCD68ED for ; Tue, 10 Oct 2023 06:30:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mkO0WLfT5Nozo3tlod4odtTfQ9+8pQpYKn8gFlicv3Y=; b=zNpgW0CKcxZ8bx ANI9kqAr10ulXiEsp2oURuWpaoyXqPTGZCoJRDDRsB0St1kTxbUG7YMX36SI0/C+cD01brZnK2Qnc 5aqj0JQbyFfyKo5td95dmI74SZ+SzDWSvJQsnRh+8kPYfrujFcnd8pwb0IBhfqCzPnPpsGUklGmRz eSMnDty+ov2mzzGx0kRNz2WqJTqk4qmFITy8/f/wmtt/ZyO2+epAyGi3JnWXkaqt+6+4v5GtjOj9U CfTLCoLN98i8wIsxSv7N2OGQEv9lfcqIHjtolAkW/oudgf48LLqaOC2NGF8OnYBrdBLOK27grZfif MH5mu+TDiQkXrbPVTx9A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qq6FW-00CaEq-2y; Tue, 10 Oct 2023 06:29:46 +0000 Received: from mail-sh.amlogic.com ([58.32.228.43]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qq6FT-00CaAY-00; Tue, 10 Oct 2023 06:29:44 +0000 Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Tue, 10 Oct 2023 14:29:34 +0800 From: Xianwei Zhao To: , , , , CC: Neil Armstrong , Jerome Brunet , Michael Turquette , "Stephen Boyd" , Rob Herring , "Krzysztof Kozlowski" , Kevin Hilman , Martin Blumenstingl , Chuan Liu , Xianwei Zhao Subject: [PATCH V2 1/4] dt-bindings: clock: add Amlogic C3 PLL clock controller bindings Date: Tue, 10 Oct 2023 14:29:14 +0800 Message-ID: <20231010062917.3624223-2-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20231010062917.3624223-1-xianwei.zhao@amlogic.com> References: <20231010062917.3624223-1-xianwei.zhao@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.98.11.200] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231009_232943_041004_42A2CCB5 X-CRM114-Status: GOOD ( 10.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the C3 PLL clock controller dt-bindings for Amlogic C3 SoC family Signed-off-by: Xianwei Zhao --- V1 -> V2: Fix errors when check dtbinding use "make dt_binding_check" --- .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 +++++++++++++++++++ .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 42 +++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h base-commit: 57b55c76aaf1ba50ecc6dcee5cd6843dc4d85239 diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml new file mode 100644 index 000000000000..a646992917b7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 serials PLL Clock Controller + +maintainers: + - Chuan Liu + +properties: + compatible: + const: amlogic,c3-pll-clkc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: input pll_in + - description: input mclk_pll_in + + clock-names: + minItems: 1 + items: + - const: pll_in + - const: mclk_pll_in + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + apb { + #address-cells = <2>; + #size-cells = <2>; + + clkc_pll: clock-controller@8000 { + compatible = "amlogic,c3-pll-clkc"; + reg = <0x0 0x8000 0x0 0x1a4>; + clocks = <&clkc_periphs CLKID_PLL_IN>, + <&clkc_periphs CLKID_MCLK_PLL_IN>; + clock-names = "pll_in", "mclk_pll_in"; + #clock-cells = <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h new file mode 100644 index 000000000000..aa731e8fae29 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H + +#define CLKID_FIXED_PLL_DCO 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV40_DIV 2 +#define CLKID_FCLK_DIV40 3 +#define CLKID_FCLK_DIV2_DIV 4 +#define CLKID_FCLK_DIV2 5 +#define CLKID_FCLK_DIV2P5_DIV 6 +#define CLKID_FCLK_DIV2P5 7 +#define CLKID_FCLK_DIV3_DIV 8 +#define CLKID_FCLK_DIV3 9 +#define CLKID_FCLK_DIV4_DIV 10 +#define CLKID_FCLK_DIV4 11 +#define CLKID_FCLK_DIV5_DIV 12 +#define CLKID_FCLK_DIV5 13 +#define CLKID_FCLK_DIV7_DIV 14 +#define CLKID_FCLK_DIV7 15 +#define CLKID_GP0_PLL_DCO 16 +#define CLKID_GP0_PLL 17 +#define CLKID_HIFI_PLL_DCO 18 +#define CLKID_HIFI_PLL 19 +#define CLKID_MCLK_PLL_DCO 20 +#define CLKID_MCLK_PLL 21 +#define CLKID_MCLK_PLL_CLK 22 +#define CLKID_MCLK0_SEL 23 +#define CLKID_MCLK0_SEL_OUT 24 +#define CLKID_MCLK0_DIV 25 +#define CLKID_MCLK0 26 +#define CLKID_MCLK1_SEL 27 +#define CLKID_MCLK1_SEL_OUT 28 +#define CLKID_MCLK1_DIV 29 +#define CLKID_MCLK1 30 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */