| Message ID | 20231010104048.1923484-2-james.clark@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: perf: Add support for event counting threshold | expand |
On 10/10/2023 11:40, James Clark wrote: > FEAT_PMUv3_TH (Armv8.8) adds two new fields to PMEVTYPER, so include > them in the mask. These aren't writable on 32 bit kernels as they are in > the high part of the register, so split the mask definition to the asm > files for each platform. > > Now where the value is used in some parts of KVM, include the asm file. > > Despite not being used on aarch32, TH and TC macros are added to the > shared header file, because they are used in arm_pmuv3.c which is > compiled for both platforms. > > Signed-off-by: James Clark <james.clark@arm.com> > --- > arch/arm/include/asm/arm_pmuv3.h | 3 +++ > arch/arm64/include/asm/arm_pmuv3.h | 4 ++++ > arch/arm64/kvm/pmu-emul.c | 1 + > arch/arm64/kvm/sys_regs.c | 1 + > include/linux/perf/arm_pmuv3.h | 3 ++- > 5 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/include/asm/arm_pmuv3.h b/arch/arm/include/asm/arm_pmuv3.h > index 72529f5e2bed..491310133d09 100644 > --- a/arch/arm/include/asm/arm_pmuv3.h > +++ b/arch/arm/include/asm/arm_pmuv3.h > @@ -9,6 +9,9 @@ > #include <asm/cp15.h> > #include <asm/cputype.h> > > +/* Mask for writable bits */ > +#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff > + > #define PMCCNTR __ACCESS_CP15_64(0, c9) > > #define PMCR __ACCESS_CP15(c9, 0, c12, 0) > diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h > index 18dc2fb3d7b7..4faf4f7385a5 100644 > --- a/arch/arm64/include/asm/arm_pmuv3.h > +++ b/arch/arm64/include/asm/arm_pmuv3.h > @@ -11,6 +11,10 @@ > #include <asm/cpufeature.h> > #include <asm/sysreg.h> > > +/* Mask for writable bits */ > +#define ARMV8_PMU_EVTYPE_MASK (0xc800ffffUL | ARMV8_PMU_EVTYPE_TH | \ > + ARMV8_PMU_EVTYPE_TC) > + > #define RETURN_READ_PMEVCNTRN(n) \ > return read_sysreg(pmevcntr##n##_el0) > static inline unsigned long read_pmevcntrn(int n) > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index 6b066e04dc5d..0666212c0c15 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -11,6 +11,7 @@ > #include <linux/perf_event.h> > #include <linux/perf/arm_pmu.h> > #include <linux/uaccess.h> > +#include <asm/arm_pmuv3.h> > #include <asm/kvm_emulate.h> > #include <kvm/arm_pmu.h> > #include <kvm/arm_vgic.h> You may want to mention in the commit description that there is no impact on the KVM emulating the Guest PMU with this change, as it ignores the fields in the upper half for setting up the attributes for the backing event. Suzuki
diff --git a/arch/arm/include/asm/arm_pmuv3.h b/arch/arm/include/asm/arm_pmuv3.h index 72529f5e2bed..491310133d09 100644 --- a/arch/arm/include/asm/arm_pmuv3.h +++ b/arch/arm/include/asm/arm_pmuv3.h @@ -9,6 +9,9 @@ #include <asm/cp15.h> #include <asm/cputype.h> +/* Mask for writable bits */ +#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff + #define PMCCNTR __ACCESS_CP15_64(0, c9) #define PMCR __ACCESS_CP15(c9, 0, c12, 0) diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h index 18dc2fb3d7b7..4faf4f7385a5 100644 --- a/arch/arm64/include/asm/arm_pmuv3.h +++ b/arch/arm64/include/asm/arm_pmuv3.h @@ -11,6 +11,10 @@ #include <asm/cpufeature.h> #include <asm/sysreg.h> +/* Mask for writable bits */ +#define ARMV8_PMU_EVTYPE_MASK (0xc800ffffUL | ARMV8_PMU_EVTYPE_TH | \ + ARMV8_PMU_EVTYPE_TC) + #define RETURN_READ_PMEVCNTRN(n) \ return read_sysreg(pmevcntr##n##_el0) static inline unsigned long read_pmevcntrn(int n) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 6b066e04dc5d..0666212c0c15 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -11,6 +11,7 @@ #include <linux/perf_event.h> #include <linux/perf/arm_pmu.h> #include <linux/uaccess.h> +#include <asm/arm_pmuv3.h> #include <asm/kvm_emulate.h> #include <kvm/arm_pmu.h> #include <kvm/arm_vgic.h> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index e92ec810d449..d0e11e684f07 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -17,6 +17,7 @@ #include <linux/printk.h> #include <linux/uaccess.h> +#include <asm/arm_pmuv3.h> #include <asm/cacheflush.h> #include <asm/cputype.h> #include <asm/debug-monitors.h> diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h index e3899bd77f5c..ec3a01502e7c 100644 --- a/include/linux/perf/arm_pmuv3.h +++ b/include/linux/perf/arm_pmuv3.h @@ -228,7 +228,8 @@ /* * PMXEVTYPER: Event selection reg */ -#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */ +#define ARMV8_PMU_EVTYPE_TH GENMASK(43, 32) +#define ARMV8_PMU_EVTYPE_TC GENMASK(63, 61) #define ARMV8_PMU_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */ /*
FEAT_PMUv3_TH (Armv8.8) adds two new fields to PMEVTYPER, so include them in the mask. These aren't writable on 32 bit kernels as they are in the high part of the register, so split the mask definition to the asm files for each platform. Now where the value is used in some parts of KVM, include the asm file. Despite not being used on aarch32, TH and TC macros are added to the shared header file, because they are used in arm_pmuv3.c which is compiled for both platforms. Signed-off-by: James Clark <james.clark@arm.com> --- arch/arm/include/asm/arm_pmuv3.h | 3 +++ arch/arm64/include/asm/arm_pmuv3.h | 4 ++++ arch/arm64/kvm/pmu-emul.c | 1 + arch/arm64/kvm/sys_regs.c | 1 + include/linux/perf/arm_pmuv3.h | 3 ++- 5 files changed, 11 insertions(+), 1 deletion(-)