From patchwork Thu Oct 12 12:34:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joey Gouly X-Patchwork-Id: 13419219 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CECF4CDB483 for ; Thu, 12 Oct 2023 12:35:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9J2PhPBfDzHRTwOqiuIOuWkJs6FRBf7JdpHTh1c2MUI=; b=biAIgPisfHf60T ItA9tv1lKHyF+Ak5QSsy7yYWDf/qgAVFczKEGXnv1qCD4bJ7uQjW0Zk0eyrjg1zLcyfGh3mLeiT9R oLTHHNvuetl4sx+oxNIG02zEq2ejjsGFO7r3Q3ntuFwiLdjyO0s/DXU7dYmwS7otK5JN6JPqwuc7o gmp7oiwKg5jcHR25EwWZ7jgIkk6L9dPAKwgBxeXfo4MvOoGo05LIsrWkLvOb74CgkzOjZZ99FJbtd Ehv+/NkI9lPRjmkF/k8NCGFtS/dQT70pBWKVCpR7AlBHEHZY1Woh/hS4Ida0Mfgp5SZVAAJuM2z/1 EnDJvVdbhy/jixRYPi0w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qquuM-000yiD-1B; Thu, 12 Oct 2023 12:35:18 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qquuI-000yh0-0q for linux-arm-kernel@lists.infradead.org; Thu, 12 Oct 2023 12:35:17 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 98A1114BF; Thu, 12 Oct 2023 05:35:50 -0700 (PDT) Received: from e124191.cambridge.arm.com (e124191.cambridge.arm.com [10.1.197.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 15AF73F5A1; Thu, 12 Oct 2023 05:35:08 -0700 (PDT) From: Joey Gouly To: linux-arm-kernel@lists.infradead.org Cc: joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, kvmarm@lists.linux.dev Subject: [PATCH v1 1/2] KVM: arm64: add nPIR{E0}_EL1 to HFG traps Date: Thu, 12 Oct 2023 13:34:58 +0100 Message-Id: <20231012123459.2820835-2-joey.gouly@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231012123459.2820835-1-joey.gouly@arm.com> References: <20231012123459.2820835-1-joey.gouly@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231012_053514_356233_60531C0D X-CRM114-Status: UNSURE ( 9.52 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org nPIR_EL1 and nPIREO_EL1 are part of the 'reverse polarity' set of bits, set them so that we disable the traps for a guest. Signed-off-by: Joey Gouly Fixes: e930694e6145 ("KVM: arm64: Restructure FGT register switching") Cc: Marc Zyngier Cc: Oliver Upton --- arch/arm64/include/asm/kvm_arm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 5882b2415596..1095c6647e96 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -344,14 +344,14 @@ */ #define __HFGRTR_EL2_RES0 (GENMASK(63, 56) | GENMASK(53, 51)) #define __HFGRTR_EL2_MASK GENMASK(49, 0) -#define __HFGRTR_EL2_nMASK (GENMASK(55, 54) | BIT(50)) +#define __HFGRTR_EL2_nMASK (GENMASK(58, 57) | GENMASK(55, 54) | BIT(50)) #define __HFGWTR_EL2_RES0 (GENMASK(63, 56) | GENMASK(53, 51) | \ BIT(46) | BIT(42) | BIT(40) | BIT(28) | \ GENMASK(26, 25) | BIT(21) | BIT(18) | \ GENMASK(15, 14) | GENMASK(10, 9) | BIT(2)) #define __HFGWTR_EL2_MASK GENMASK(49, 0) -#define __HFGWTR_EL2_nMASK (GENMASK(55, 54) | BIT(50)) +#define __HFGWTR_EL2_nMASK (GENMASK(58, 57) | GENMASK(55, 54) | BIT(50)) #define __HFGITR_EL2_RES0 GENMASK(63, 57) #define __HFGITR_EL2_MASK GENMASK(54, 0)