| Message ID | 20231016113002.15929-2-jay.buddhabhatti@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | update for versal net platform | expand |
Quoting Jay Buddhabhatti (2023-10-16 04:30:01) > Currently zynqmp clock driver is not calculating closest mux rate and > because of that Linux is not setting proper frequency for CPU and > not able to set given frequency for dynamic frequency scaling. > > E.g., In current logic initial acpu clock parent and frequency as below > apll1 0 0 0 2199999978 0 0 50000 Y > acpu0_mux 0 0 0 2199999978 0 0 50000 Y > acpu0_idiv1 0 0 0 2199999978 0 0 50000 Y > acpu0 0 0 0 2199999978 0 0 50000 Y > > After changing acpu frequency to 549999994 Hz using CPU freq scaling its > selecting incorrect parent which is not closest frequency. > rpll_to_xpd 0 0 0 1599999984 0 0 50000 Y > acpu0_mux 0 0 0 1599999984 0 0 50000 Y > acpu0_div1 0 0 0 533333328 0 0 50000 Y > acpu0 0 0 0 533333328 0 0 50000 Y > > Parent should remain same since 549999994 = 2199999978 / 4. > > So use __clk_mux_determine_rate_closest() generic function to calculate > closest rate for mux clock. After this change its selecting correct > parent and correct clock rate. > apll1 0 0 0 2199999978 0 0 50000 Y > acpu0_mux 0 0 0 2199999978 0 0 50000 Y > acpu0_div1 0 0 0 549999995 0 0 50000 Y > acpu0 0 0 0 549999995 0 0 50000 Y > > Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> > --- Any Fixes tag here?
Hi Stephen, > -----Original Message----- > From: Stephen Boyd <sboyd@kernel.org> > Sent: Tuesday, October 24, 2023 9:09 AM > To: Buddhabhatti, Jay <jay.buddhabhatti@amd.com>; Simek, Michal > <michal.simek@amd.com>; mturquette@baylibre.com > Cc: linux-clk@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; Buddhabhatti, Jay <jay.buddhabhatti@amd.com> > Subject: Re: [PATCH RESEND 1/2] drivers: clk: zynqmp: calculate closest mux > rate > > Quoting Jay Buddhabhatti (2023-10-16 04:30:01) > > Currently zynqmp clock driver is not calculating closest mux rate and > > because of that Linux is not setting proper frequency for CPU and not > > able to set given frequency for dynamic frequency scaling. > > > > E.g., In current logic initial acpu clock parent and frequency as below > > apll1 0 0 0 2199999978 0 0 50000 Y > > acpu0_mux 0 0 0 2199999978 0 0 50000 Y > > acpu0_idiv1 0 0 0 2199999978 0 0 50000 Y > > acpu0 0 0 0 2199999978 0 0 50000 Y > > > > After changing acpu frequency to 549999994 Hz using CPU freq scaling > > its selecting incorrect parent which is not closest frequency. > > rpll_to_xpd 0 0 0 1599999984 0 0 50000 Y > > acpu0_mux 0 0 0 1599999984 0 0 50000 Y > > acpu0_div1 0 0 0 533333328 0 0 50000 Y > > acpu0 0 0 0 533333328 0 0 50000 Y > > > > Parent should remain same since 549999994 = 2199999978 / 4. > > > > So use __clk_mux_determine_rate_closest() generic function to > > calculate closest rate for mux clock. After this change its selecting > > correct parent and correct clock rate. > > apll1 0 0 0 2199999978 0 0 50000 Y > > acpu0_mux 0 0 0 2199999978 0 0 50000 Y > > acpu0_div1 0 0 0 549999995 0 0 50000 Y > > acpu0 0 0 0 549999995 0 0 50000 Y > > > > Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> > > --- > > Any Fixes tag here? [Jay] Sure I will add fixes tag. Thanks, Jay
diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c index 60359333f26d..9b5d3050b742 100644 --- a/drivers/clk/zynqmp/clk-mux-zynqmp.c +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c @@ -89,7 +89,7 @@ static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index) static const struct clk_ops zynqmp_clk_mux_ops = { .get_parent = zynqmp_clk_mux_get_parent, .set_parent = zynqmp_clk_mux_set_parent, - .determine_rate = __clk_mux_determine_rate, + .determine_rate = __clk_mux_determine_rate_closest, }; static const struct clk_ops zynqmp_clk_mux_ro_ops = {
Currently zynqmp clock driver is not calculating closest mux rate and because of that Linux is not setting proper frequency for CPU and not able to set given frequency for dynamic frequency scaling. E.g., In current logic initial acpu clock parent and frequency as below apll1 0 0 0 2199999978 0 0 50000 Y acpu0_mux 0 0 0 2199999978 0 0 50000 Y acpu0_idiv1 0 0 0 2199999978 0 0 50000 Y acpu0 0 0 0 2199999978 0 0 50000 Y After changing acpu frequency to 549999994 Hz using CPU freq scaling its selecting incorrect parent which is not closest frequency. rpll_to_xpd 0 0 0 1599999984 0 0 50000 Y acpu0_mux 0 0 0 1599999984 0 0 50000 Y acpu0_div1 0 0 0 533333328 0 0 50000 Y acpu0 0 0 0 533333328 0 0 50000 Y Parent should remain same since 549999994 = 2199999978 / 4. So use __clk_mux_determine_rate_closest() generic function to calculate closest rate for mux clock. After this change its selecting correct parent and correct clock rate. apll1 0 0 0 2199999978 0 0 50000 Y acpu0_mux 0 0 0 2199999978 0 0 50000 Y acpu0_div1 0 0 0 549999995 0 0 50000 Y acpu0 0 0 0 549999995 0 0 50000 Y Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> --- drivers/clk/zynqmp/clk-mux-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)