From patchwork Wed Oct 18 03:00:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 13426250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18AC5CDB482 for ; Wed, 18 Oct 2023 03:00:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=ax4RIo6L0uOitb1Ld7mLEd5aWGdJCZsGvfg0RXlLLCI=; b=TwNpF0mE/iKcBv KsTIE2yhnH/AGdRbqIcc+fwMinmqJTgbWt7/mt9BhcCP+efwn1chKui3/CQ9JLgNt6Bb7x/jCRJuP Y6HKq1RjfmrP5htJyknTAPDX7uKjlWCu1B3romjebX95xsGrQKa/1WBM1sKV/D0Chy1s7EbjEOK+j tA3lAmTW43fHFxc0pVOJVXeiGAqf0Qye/swW+CYrek9mNsTeaavFclD6CWMHDEI9TiUTEPjTFlOGF t7qvGd+ilVlonq0WZhZLCfyIBq/ejdKhsfmp/e4VPjvhZyf1GWdzCxL6JUdLPvB3G2tVk+NzLk8mt qFFlQInl0P4hqghd8nIw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qswnP-00Dd5H-2u; Wed, 18 Oct 2023 03:00:31 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qswnM-00Dd4K-0a for linux-arm-kernel@lists.infradead.org; Wed, 18 Oct 2023 03:00:30 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 316B22F4; Tue, 17 Oct 2023 20:01:01 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 846AF3F5A1; Tue, 17 Oct 2023 20:00:17 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Oliver Upton , Marc Zyngier , linux-kernel@vger.kernel.org Subject: [PATCH] arm64: Independently update HDFGRTR_EL2 and HDFGWTR_EL2 Date: Wed, 18 Oct 2023 08:30:07 +0530 Message-Id: <20231018030007.1968317-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231017_200028_292507_B842112A X-CRM114-Status: GOOD ( 10.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently PMSNEVFR_EL1 system register read, and write access EL2 traps are disabled, via setting the same bit (i.e 62) in HDFGRTR_EL2, and HDFGWTR_EL2 respectively. Although very similar, bit fields are not exact same in these two EL2 trap configure registers particularly when it comes to read-only or write-only accesses such as ready-only 'HDFGRTR_EL2.nBRBIDR' which needs to be set while enabling BRBE on NVHE platforms. Using the exact same bit mask fields for both these trap register risk writing into their RESERVED areas, which is undesirable. Cc: Catalin Marinas Cc: Will Deacon Cc: Oliver Upton Cc: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- This applies on v6.6-rc6. I guess it should be okay to use 'x2' as it is in the clobbered register list for init_el2_state() function. But please do let me know otherwise. arch/arm64/include/asm/el2_setup.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 899b5c10f84c..c534afb1a30d 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -206,16 +206,19 @@ cbz x1, .Lskip_fgt_\@ mov x0, xzr + mov x2, xzr mrs x1, id_aa64dfr0_el1 ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 cmp x1, #3 b.lt .Lset_debug_fgt_\@ + /* Disable PMSNEVFR_EL1 read and write traps */ - orr x0, x0, #(1 << 62) + orr x0, x0, #HDFGRTR_EL2_nPMSNEVFR_EL1_MASK + orr x2, x2, #HDFGWTR_EL2_nPMSNEVFR_EL1_MASK .Lset_debug_fgt_\@: msr_s SYS_HDFGRTR_EL2, x0 - msr_s SYS_HDFGWTR_EL2, x0 + msr_s SYS_HDFGWTR_EL2, x2 mov x0, xzr mrs x1, id_aa64pfr1_el1