| Message ID | 20231019100857.108883-1-lpieralisi@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | irqchip/gic-v3: Fix ICC_ASG1R_EL1 typo in comment | expand |
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index eedfa8e9f077..3dc41bbf494a 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -1236,7 +1236,7 @@ static void gic_cpu_sys_reg_init(void) /** * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, - * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED + * writing ICC_SGI1R_EL1 register with RS != 0 is a CONSTRAINED * UNPREDICTABLE choice of : * - The write is ignored. * - The RS field is treated as 0.
In the code probing the GIC RS feature, a log was added with a comment referring to the ICC_ASGI1R_EL1 register, that is actually referring to the ICC_SGI1R_EL1 register (since the kernel does not program ICC_ASGI1R_EL1). Fix the typo to prevent confusion. Fixes: eda0d04acc5e ("irqchip/gic-v3: Add support for Range Selector (RS) feature") Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: Marc Zyngier <maz@kernel.org> --- drivers/irqchip/irq-gic-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)