From patchwork Thu Oct 19 10:08:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 13428544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 264E9CDB482 for ; Thu, 19 Oct 2023 10:09:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=if4eDqXtBch8YWOxo3/v4dnS6UHtLelXESpWmSPJdKc=; b=X6XQSLYEtRnNua o9svmtog/ld/CTbNn490ORnk81U2ZlSZIlSU3uWcAbpF4clRs2CUDQHsmX4MAbZxyHr3qu/bgJVE3 928udXdDIYk+Nq+hWI9qi5eJWMoMIGXc65WvOvoYYB+eiZBsb1eyCnQvK94xzJZeEuTi+mlXfpc1E AasDnJ9LEhNKVU0szkMcmWBFPuR7ekqnmpAiARQvR8wu+QY+xhiwItWZ/me8er+zeQJ6Rr9p3hH/G i5USeKqq7jI11dYJecRVvorYdN4SWu6xnQy/xIUszSRYnMto7WzAHl9NW3kfNHCd00X2gjMueMlbu ASjeXHLcioPuy5upYqAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qtPxu-00Gual-0D; Thu, 19 Oct 2023 10:09:18 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qtPxl-00GuWj-21 for linux-arm-kernel@lists.infradead.org; Thu, 19 Oct 2023 10:09:11 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id EB045CE2AC7 for ; Thu, 19 Oct 2023 10:09:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0310AC433C7; Thu, 19 Oct 2023 10:09:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697710144; bh=ZARZSYoZeLIBOv9/lGEb8D3fSfUQQF8vvvV/ODx7Xic=; h=From:To:Cc:Subject:Date:From; b=r6K77C0fduGCTEjBpbTYAyVbsryta2PXrqSItMY+vNS747GKnWGU1XNWvtLq86VZl qbxCUQjPaGIuSIT/935S0lCvSK6G+PhQM2Gj9bTHFuPGNTfLafwKkWff2CSKzyQKvv Gs5SwQWjebovD2vaJa8UVFZyvHBHNM88k/n30ZfqGQPVehc9kwaPt9iAbJPTGiLqtB dCeDyY/SJZDyOPauRclwcNlj/DUYzk898yM/eRUDkyeejMJf9jyHr3yxjzttzmImYI RBLPWr2y6fj8IBcq+NJvXU7nPGoDbk6sbMvejU/lpBojp0AvSbePX3jLgmN2tqQGpr bRe74kQoidJSg== From: Lorenzo Pieralisi To: linux-arm-kernel@lists.infradead.org Cc: Lorenzo Pieralisi , Marc Zyngier Subject: [PATCH] irqchip/gic-v3: Fix ICC_ASG1R_EL1 typo in comment Date: Thu, 19 Oct 2023 12:08:57 +0200 Message-Id: <20231019100857.108883-1-lpieralisi@kernel.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231019_030910_164048_B13EF02A X-CRM114-Status: GOOD ( 12.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In the code probing the GIC RS feature, a log was added with a comment referring to the ICC_ASGI1R_EL1 register, that is actually referring to the ICC_SGI1R_EL1 register (since the kernel does not program ICC_ASGI1R_EL1). Fix the typo to prevent confusion. Fixes: eda0d04acc5e ("irqchip/gic-v3: Add support for Range Selector (RS) feature") Signed-off-by: Lorenzo Pieralisi Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index eedfa8e9f077..3dc41bbf494a 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -1236,7 +1236,7 @@ static void gic_cpu_sys_reg_init(void) /** * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, - * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED + * writing ICC_SGI1R_EL1 register with RS != 0 is a CONSTRAINED * UNPREDICTABLE choice of : * - The write is ignored. * - The RS field is treated as 0.