From patchwork Thu Oct 19 16:55:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 13429537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A1B9CDB465 for ; Thu, 19 Oct 2023 16:56:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0BvDD8SUkX5Fjw2IMjXTRfmL3TZj2USaVJvrdEhkR0k=; b=ideB9ApssnwM74 r9lbXXFLoH4ulMOpC0zhTNu77v+4SmnFs3Kecf7EMGzlLD4HYtWxiZKRVouUTG4e6h5OzDQXC0fqW +kAzhBq/Ff/7IFdkdej+WhgVYh/mflyXUhiYaMJAbICJ/zYO6u3TH9HCB2TdxpiT+TSTp1kD45c6h LfQHrIVG2E5/F/X0tLH/0+5D9iMtyUF1Vfp3pYfcgqsEJtUa35zFOZjzJFjzPRoc/trAq/GVR/5UM NBHBKpZ5nRVoa2liZe1CmzTci8nGq26oJcqLKKd3zNJvxulezavBGfrIZt3DRPx3vyqzU+pRfT0IR 70Ek1Zd5F4GAc0btxBfw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qtWJo-000MIy-2m; Thu, 19 Oct 2023 16:56:20 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qtWJj-000MGp-1u for linux-arm-kernel@lists.infradead.org; Thu, 19 Oct 2023 16:56:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A9AFE2F4; Thu, 19 Oct 2023 09:56:53 -0700 (PDT) Received: from e127643.arm.com (unknown [10.57.67.150]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 88BC53F5A1; Thu, 19 Oct 2023 09:56:09 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, maz@kernel.org, suzuki.poulose@arm.com Cc: broonie@kernel.org, James Clark , Oliver Upton , James Morse , Zenghui Yu , Catalin Marinas , Will Deacon , Mike Leach , Leo Yan , Alexander Shishkin , Anshuman Khandual , Rob Herring , Jintack Lim , Fuad Tabba , Kristina Martsenko , Akihiko Odaki , Joey Gouly , linux-kernel@vger.kernel.org Subject: [PATCH v3 3/6] arm64: KVM: Add iflag for FEAT_TRF Date: Thu, 19 Oct 2023 17:55:01 +0100 Message-Id: <20231019165510.1966367-4-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019165510.1966367-1-james.clark@arm.com> References: <20231019165510.1966367-1-james.clark@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231019_095615_723072_7A725960 X-CRM114-Status: GOOD ( 16.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add an extra iflag to signify if the TRFCR register is accessible. Because TRBE requires FEAT_TRF, DEBUG_STATE_SAVE_TRBE still has the same behavior even though it's only set when FEAT_TRF is present. The following holes are left in struct kvm_vcpu_arch, but there aren't enough other 8 bit fields to rearrange it to leave any hole smaller than 7 bytes: u8 cflags; /* 2292 1 */ /* XXX 1 byte hole, try to pack */ u16 iflags; /* 2294 2 */ u8 sflags; /* 2296 1 */ bool pause; /* 2297 1 */ /* XXX 6 bytes hole, try to pack */ Signed-off-by: James Clark Reviewed-by: Suzuki K Poulose --- arch/arm64/include/asm/kvm_host.h | 4 +++- arch/arm64/kvm/debug.c | 22 ++++++++++++++++++---- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 7c82927ddaf2..0f0bf8e641bd 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -535,7 +535,7 @@ struct kvm_vcpu_arch { u8 cflags; /* Input flags to the hypervisor code, potentially cleared after use */ - u8 iflags; + u16 iflags; /* State flags for kernel bookkeeping, unused by the hypervisor code */ u8 sflags; @@ -741,6 +741,8 @@ struct kvm_vcpu_arch { #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) /* vcpu running in HYP context */ #define VCPU_HYP_CONTEXT __vcpu_single_flag(iflags, BIT(7)) +/* Save trace filter controls */ +#define DEBUG_STATE_SAVE_TRFCR __vcpu_single_flag(iflags, BIT(8)) /* SVE enabled for host EL0 */ #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index 8725291cb00a..20cdd40b3c42 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -331,14 +331,28 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu) !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(PMBIDR_EL1_P_SHIFT))) vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_SPE); - /* Check if we have TRBE implemented and available at the host */ - if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceBuffer_SHIFT) && - !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_P)) - vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE); + /* + * Save TRFCR on nVHE if FEAT_TRF (TraceFilt) exists. This will be + * done in cases where use of TRBE doesn't completely disable trace and + * handles the exclude_host/exclude_guest rules of the trace session. + */ + if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT)) { + vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRFCR); + /* + * Check if we have TRBE implemented and available at the host. If it's + * in use at the time of guest switch it will need to be disabled and + * then restored. The architecture mandates FEAT_TRF with TRBE, so we + * only need to check for TRBE after TRF. + */ + if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceBuffer_SHIFT) && + !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_P)) + vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE); + } } void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu) { vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_SPE); vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRBE); + vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRFCR); }