From patchwork Fri Oct 20 14:57:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 13430850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7240C0032E for ; Fri, 20 Oct 2023 14:57:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=e2h0vzIGROiHHdoc3RPzY/W1N2szJQP5AudfKBP656s=; b=a8+51kG0l2rLNd ppZqMQF6vbO2YiUTYNrhFsAS4MLAuFnv2kkrAMmYoH/0lf3NpWKFkbFnJ8PrK8MeifN9Xs9XxggGy dIfEmDHzFpE8kFmdjk4rPTtB8n4C48E3tWHQOyojBzjaJrX3h56g00geg2t7VKLbTt74ywFUvBjoO QDW12yFRXnOxvIhgGh9CTaQ7jqRba7thpGlEKQk2okOBGCJ3gCfia5gTG5Qu/IkPyP1S8rPp7GbGX QLuYFZJ/1GTEO6s3mUs33u//7vIePizEtL9Fw8cc52DyG5sQpU9egYtrkSijjfPld1Ac5z9FZwVLU uDr8vxGUgn6TIzB1ARuQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qtqwN-002Xbt-2o; Fri, 20 Oct 2023 14:57:31 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qtqwA-002XXi-03 for linux-arm-kernel@lists.infradead.org; Fri, 20 Oct 2023 14:57:20 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 89C201570; Fri, 20 Oct 2023 07:57:56 -0700 (PDT) Received: from donnerap.arm.com (donnerap.manchester.arm.com [10.32.101.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C41023F762; Fri, 20 Oct 2023 07:57:13 -0700 (PDT) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland , Chen-Yu Tsai Cc: Marc Zyngier , Piotr Oniszczuk , linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 2/2] arm64: dts: allwinner: h616: add Orange Pi Zero 2W support Date: Fri, 20 Oct 2023 15:57:06 +0100 Message-Id: <20231020145706.705420-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231020145706.705420-1-andre.przywara@arm.com> References: <20231020145706.705420-1-andre.przywara@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231020_075718_188266_FF1A9BE2 X-CRM114-Status: GOOD ( 17.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Orange Pi Zero 2W is a board based on the Allwinner H618 SoC. It uses the RaspberryPi Zero form factor, with an optional expansion board, connected via an FPC connector, to provide more connectors. The base board features: - Allwinner H618 SoC (quad Cortex-A53 cores, with 1MB L2 cache) - 1, 2 or 4GB of LPDDR4 DRAM - SD card socket - two USB-C sockets, one UFP, one DFP - HDMI connector - (yet unsupported) WiFi module - 16 MiB SPI flash - power supply via the UFP USB-C port The FPC connector provides access to two more USB host ports, Fast Ethernet, some GPIOs, Audio Line out and the IR receiver pin. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- .../allwinner/sun50i-h618-orangepi-zero2w.dts | 176 ++++++++++++++++++ 1 file changed, 176 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts new file mode 100644 index 0000000000000..21ca1977055d9 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include +#include +#include + +/ { + model = "OrangePi Zero 2W"; + compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h618"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_vcc3v3: vcc3v3 { + /* SY8089 DC/DC converter */ + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v>; + regulator-always-on; + }; +}; + +&ehci1 { + status = "okay"; +}; + +/* USB 2 & 3 are on the FPC connector (or the exansion board) */ + +&mmc0 { + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pf-supply = <®_dldo1>; /* internally via VCC-IO */ + vcc-pg-supply = <®_aldo1>; + vcc-ph-supply = <®_dldo1>; /* internally via VCC-IO */ + vcc-pi-supply = <®_dldo1>; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + /* Supplies VCC-PLL and DRAM */ + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Supplies VCC-IO, so needs to be always on. */ + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v>; + status = "okay"; +};