| Message ID | 20231025165058.31697-5-laurent.pinchart@ideasonboard.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: freescale: Add Variscite i.MX8MP DART8MCustomBoard v2 | expand |
On Wed, Oct 25, 2023 at 07:50:58PM +0300, Laurent Pinchart wrote: > Add a DT overlay for the Variscite i.MX8MP DT8MCustomBoard that models > the GKTW70SDAE4SE LVDS panel found in the evaluation kit. > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> It doesn't apply to imx/dt64 branch, and I managed to manually apply it. However, here is what I'm getting from 'make ARCH=arm64 dtbs'. ../arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso:54.3-16: Warning (reg_format): /fragment@1/__overlay__/touch@38:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtbo: Warning (pci_device_reg): Failed prerequisite 'reg_format' arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtbo: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtbo: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtbo: Warning (spi_bus_reg): Failed prerequisite 'reg_format' ../arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso:52.11-68.4: Warning (avoid_default_addr_size): /fragment@1/__overlay__/touch@38: Relying on default #address-cells value ../arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso:52.11-68.4: Warning (avoid_default_addr_size): /fragment@1/__overlay__/touch@38: Relying on default #size-cells value arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtbo: Warning (graph_port): /fragment@3: graph port node name should be 'port' ../arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso:85.15-87.3: Warning (graph_endpoint): /fragment@3/__overlay__: graph endpoint node name should be 'endpoint' ../arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso:85.15-87.3: Warning (graph_endpoint): /fragment@3/__overlay__: graph connection to node '/fragment@0/__overlay__/panel/port/endpoint' is not bidirectional Shawn
Hi Shawn, On Mon, Nov 27, 2023 at 11:16:31AM +0800, Shawn Guo wrote: > On Wed, Oct 25, 2023 at 07:50:58PM +0300, Laurent Pinchart wrote: > > Add a DT overlay for the Variscite i.MX8MP DT8MCustomBoard that models > > the GKTW70SDAE4SE LVDS panel found in the evaluation kit. > > > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > It doesn't apply to imx/dt64 branch, and I managed to manually apply it. I'll submit a v3 based on that branch. > However, here is what I'm getting from 'make ARCH=arm64 dtbs'. > > ../arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso:54.3-16: Warning (reg_format): /fragment@1/__overlay__/touch@38:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) > arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtbo: Warning (pci_device_reg): Failed prerequisite 'reg_format' > arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtbo: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' > arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtbo: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' > arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtbo: Warning (spi_bus_reg): Failed prerequisite 'reg_format' > ../arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso:52.11-68.4: Warning (avoid_default_addr_size): /fragment@1/__overlay__/touch@38: Relying on default #address-cells value > ../arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso:52.11-68.4: Warning (avoid_default_addr_size): /fragment@1/__overlay__/touch@38: Relying on default #size-cells value > arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtbo: Warning (graph_port): /fragment@3: graph port node name should be 'port' > ../arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso:85.15-87.3: Warning (graph_endpoint): /fragment@3/__overlay__: graph endpoint node name should be 'endpoint' > ../arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso:85.15-87.3: Warning (graph_endpoint): /fragment@3/__overlay__: graph connection to node '/fragment@0/__overlay__/panel/port/endpoint' is not bidirectional Is that unexpected ? My understanding is that the DT compiler doesn't have enough information when compiling an overlay to validate the device tree, as it looks at the overlay only, without considering the base DT on which the overlay will apply.
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 19637302397f..20514cb1c505 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -150,6 +150,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb +imx8mp-var-dart-panel-gktw70sdae4se-dtbs := imx8mp-var-dart-dt8mcustomboard-v2.dtb imx8mp-var-dart-panel-gktw70sdae4se.dtbo imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo @@ -162,6 +163,7 @@ imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice- imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo imx8mp-venice-gw74xx-rpidsi-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-rpidsi.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-dart-panel-gktw70sdae4se.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rpidsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso b/arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso new file mode 100644 index 000000000000..d5f61e157bc2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2020-2021 Variscite Ltd. + * Copyright 2023 Ideas on Board Oy + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx8mp-pinfunc.h" + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 1000000 0>; + }; + + panel { + compatible = "sgd,gktw70sdae4se", "panel-lvds"; + backlight = <&backlight>; + width-mm = <153>; + height-mm = <87>; + label = "gktw70sdae4se"; + data-mapping = "jeida-24"; + + panel-timing { + clock-frequency = <29232000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <29>; + vfront-porch = <13>; + hsync-len = <48>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&i2c2 { + touch@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + + reset-gpios = <&gpio_exp_2 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + +&lcdif2 { + /* + * The pixel clock should be configured by the lcdif driver, but the + * clock frequency propagation in the clock framework stops at the PIX2 + * clock and doesn't reach the VIDEO_PLL1 clock. As a workaround, set + * the VIDEO_PLL1 rate manually. + * + * For a 60Hz refresh rate, the panel requires a pixel clock of 29.232 + * MHz. The LVDS clock frequency is 7 times higher, or 204.624 MHz. + */ + assigned-clock-rates = <0>, <204624000>; + status = "okay"; +}; + +&ldb_lvds_ch0 { + remote-endpoint = <&panel_in>; +}; + +&lvds_bridge { + status = "okay"; +}; + +&iomuxc { + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x16 + >; + }; +};
Add a DT overlay for the Variscite i.MX8MP DT8MCustomBoard that models the GKTW70SDAE4SE LVDS panel found in the evaluation kit. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx8mp-var-dart-panel-gktw70sdae4se.dtso | 99 +++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-var-dart-panel-gktw70sdae4se.dtso