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Mon, 30 Oct 2023 18:06:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Oct 2023 18:06:28 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , Moudy Ho Subject: [PATCH v8 07/12] media: platform: mtk-mdp3: extend GCE event waiting in RDMA and WROT Date: Mon, 30 Oct 2023 18:06:21 +0800 Message-ID: <20231030100626.12564-8-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030100626.12564-1-moudy.ho@mediatek.com> References: <20231030100626.12564-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--9.856400-8.000000 X-TMASE-MatchedRID: mJkk328f4R4mNHlC7DQV5eKXavbHY/C1dG7bDJL8qEe0rcU5V/oSe/dQ 3ETtBTk8CTzLWkg2tvC1JEhwlIePJTA9KOtcb1F9t1AhvyEKdj67nrAU9KQxUWJkJOQVCIpw8Fh GjTp5WPdMtAAmLKD7vIAy6p60ZV62fJ5/bZ6npdiyO81X3yak8zoaIvcHGxrgFryEq+08+r2Z65 A3tOPbiTs3QfOh8jRbxiEBH2WVH+V+3BndfXUhXQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--9.856400-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 2C882936CF921A7812A1A769AC0AEB12535E232FAF777D03B33D04F19B3DBAC72000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231030_030636_112234_4707161A X-CRM114-Status: GOOD ( 15.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Support for multiple RDMA/WROT waits for GCE events. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/mdp3/mdp_cfg_data.c | 2 ++ .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 27 +++++++++++++------ .../platform/mediatek/mdp3/mtk-mdp3-core.h | 2 ++ 3 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c index 6f77c33074ec..3834efe54e17 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -56,8 +56,10 @@ static const struct mdp_platform_config mt8183_plat_cfg = { .rdma_support_10bit = true, .rdma_rsz1_sram_sharing = true, .rdma_upsample_repeat_only = true, + .rdma_event_num = 1, .rsz_disable_dcm_small_sample = false, .wrot_filter_constraint = false, + .wrot_event_num = 1, }; static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = { diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 93df2e013438..ed6092e1666f 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -251,14 +251,20 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, static int wait_rdma_event(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) { + const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); struct device *dev = &ctx->comp->mdp_dev->pdev->dev; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; - if (ctx->comp->alias_id == 0) - MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); - else - dev_err(dev, "Do not support RDMA1_DONE event\n"); + if (!mdp_cfg) + return -EINVAL; + + if (ctx->comp->alias_id >= mdp_cfg->rdma_event_num) { + dev_err(dev, "Invalid RDMA event %d\n", ctx->comp->alias_id); + return -EINVAL; + } + + MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); /* Disable RDMA */ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0)); @@ -553,10 +559,15 @@ static int wait_wrot_event(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; - if (ctx->comp->alias_id == 0) - MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); - else - dev_err(dev, "Do not support WROT1_DONE event\n"); + if (!mdp_cfg) + return -EINVAL; + + if (ctx->comp->alias_id >= mdp_cfg->wrot_event_num) { + dev_err(dev, "Invalid WROT event %d!\n", ctx->comp->alias_id); + return -EINVAL; + } + + MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); if (mdp_cfg && mdp_cfg->wrot_filter_constraint) MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0, diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index 22d1b17ef2fc..e57c415a1c78 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -49,8 +49,10 @@ struct mdp_platform_config { bool rdma_support_10bit; bool rdma_rsz1_sram_sharing; bool rdma_upsample_repeat_only; + u32 rdma_event_num; bool rsz_disable_dcm_small_sample; bool wrot_filter_constraint; + u32 wrot_event_num; }; /* indicate which mutex is used by each pipepline */