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([79.115.63.76]) by smtp.gmail.com with ESMTPSA id gq23-20020a170906e25700b0099e12a49c8fsm2206415ejb.173.2023.11.01.02.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 02:43:37 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: miquel.raynal@bootlin.com, richard@nod.at, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, Tudor Ambarus Subject: [PATCH 5/6] mtd: spi-nor: remove NO_CHIP_ERASE flag Date: Wed, 1 Nov 2023 11:43:24 +0200 Message-Id: <20231101094325.95851-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231101094325.95851-1-tudor.ambarus@linaro.org> References: <20231101094325.95851-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1896; i=tudor.ambarus@linaro.org; h=from:subject; bh=qodvSZkEdT/igPH1EKd80cKPj1l48lT2Qmj2i6tTMmA=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlQh297pYvrWy0+J/XmGtkqJPAYiJOikqbF8ux0 v76yx1hSdWJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZUIdvQAKCRBLVU9HpY0U 6cqOB/4z7qYxEy4qgfj3OB5uYfKpxaXci8KkLPIv8SXh8MBTaeIQcqrhHfcQAx4L2STdEPIt6rv j6Kw0HI8qJZUKNyJVKoljSkhMxdhgypg9+9CTa5uQgqpl51xrligCV81y67MqV8qKrk5Xex7yWO h21H2PhNAuHpufFxU90FoT3sPsAXtaNfdML3zEAJHvmMLFBBgJtYWd7c3bkxPI9un0yJXozBraT KXSuH+e6OgVf3n/QEjFZROVuwWs4gjRZULyvJXWFzeqIjNfTzSmj8j4H9d9djzSeBalkXef+/tP gTTOLUtreXgu6KE4MWUsJlNEMiqYLOhHEqw2TaM1sBI15siU X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_024340_305090_41847CBD X-CRM114-Status: GOOD ( 12.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There's no flash using it and we'd like to rely instead on SFDP data, thus remove it. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 3 --- drivers/mtd/spi-nor/core.h | 8 +++----- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 360fce7ffe82..b9829a1ed192 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2862,9 +2862,6 @@ static void spi_nor_init_flags(struct spi_nor *nor) nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; } - if (flags & NO_CHIP_ERASE) - nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; - if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 && !nor->controller_ops) nor->flags |= SNOR_F_RWW; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index f681a139772f..65207c83b751 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -489,7 +489,6 @@ struct spi_nor_id { * Usually these will power-up in a write-protected * state. * SPI_NOR_NO_ERASE: no erase command needed. - * NO_CHIP_ERASE: chip does not support chip erase. * SPI_NOR_NO_FR: can't do fastread. * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program. * SPI_NOR_RWW: flash supports reads while write. @@ -539,10 +538,9 @@ struct flash_info { #define SPI_NOR_BP3_SR_BIT6 BIT(4) #define SPI_NOR_SWP_IS_VOLATILE BIT(5) #define SPI_NOR_NO_ERASE BIT(6) -#define NO_CHIP_ERASE BIT(7) -#define SPI_NOR_NO_FR BIT(8) -#define SPI_NOR_QUAD_PP BIT(9) -#define SPI_NOR_RWW BIT(10) +#define SPI_NOR_NO_FR BIT(7) +#define SPI_NOR_QUAD_PP BIT(8) +#define SPI_NOR_RWW BIT(9) u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0)