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([79.115.63.76]) by smtp.gmail.com with ESMTPSA id gq23-20020a170906e25700b0099e12a49c8fsm2206415ejb.173.2023.11.01.02.43.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 02:43:38 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: miquel.raynal@bootlin.com, richard@nod.at, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, Tudor Ambarus Subject: [PATCH 6/6] mtd: spi-nor: micron-st: Add support for mt25qu01g Date: Wed, 1 Nov 2023 11:43:25 +0200 Message-Id: <20231101094325.95851-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231101094325.95851-1-tudor.ambarus@linaro.org> References: <20231101094325.95851-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2847; i=tudor.ambarus@linaro.org; h=from:subject; bh=FN95MDStU0W7lUTO984uRiZPl3auH/CwE9nBkCd1f7s=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlQh29Tu73VMwCQWa+iaS8s1otBhT4eRYpvt5uW 8pnLMmay6qJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZUIdvQAKCRBLVU9HpY0U 6bJgB/9aae6lW7+7fwmO4f4dKxTFCYVv1Ng+WuqbR/MGbOH9XNls7JQIALP02AXbq9waFwyRn0O Gqjua1QcLfXptTip1ychKMMCHmrNTQuz3iQXeyc6iChNIyA666ZxSTr1TKJhsCYsNthoxl2KOkq XLFgYqj3FGVgh/rw/n/RGmHaSoPBpG4ubtNwrHuAyn3oqan3n5Xf8JJJQbJQSDFvUABt7ShNjuC bnfZfyCrgt4OfqxjK0GsCSIweU3oWnLFNVIC/0hHXkaHLcDtpq07Dzl45FofjxBHh9b4vFI0kB4 BFX56yds7XpnFMq3KvnQAW/19e//+iJxivANgSocxILTXXPB X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_024340_033413_762DE3D8 X-CRM114-Status: GOOD ( 12.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Fabio Estevam Add support for the MT25QU01G 128MB Micron Serial NOR Flash Memory model. Datasheet: https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_01g_bbb_0.pdf Tested on a i.MX8MP based board: # dmesg | grep spi-nor spi-nor spi0.0: mt25qu01g (131072 Kbytes) # cat /proc/mtd dev: size erasesize name mtd0: 08000000 00001000 "30bb0000.spi" ~# cat /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/jedec_id 20bb21104400 ~# cat /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/manufacturer st ~# cat /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/partname mt25qu01g ~# xxd -p /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp 53464450060101ff00060110300000ff84000102800000ffffffffffffff ffffffffffffffffffffffffffffffffffffe520fbffffffff3f29eb276b 273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e 03e1ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff ffffffffffffffffffe7ffff21dcffff ~# md5sum /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp 9d28d1b11de8b15ba9152644219d9a78 /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp Signed-off-by: Fabio Estevam [ta: introduce die erase] Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/micron-st.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 8706ef841375..6d8dd6bfbf69 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -203,10 +203,24 @@ static int st_nor_four_die_late_init(struct spi_nor *nor) return 0; } +static int st_nor_two_die_late_init(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params = nor->params; + + params->chip_erase_opcode = SPINOR_OP_MT_CHIP_ERASE; + params->n_dice = 2; + + return 0; +} + static struct spi_nor_fixups n25q00_fixups = { .late_init = st_nor_four_die_late_init, }; +static struct spi_nor_fixups mt25q01_fixups = { + .late_init = st_nor_two_die_late_init, +}; + static struct spi_nor_fixups mt25q02_fixups = { .late_init = st_nor_four_die_late_init, }; @@ -449,6 +463,11 @@ static const struct flash_info st_nor_parts[] = { SPI_NOR_BP3_SR_BIT6, .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags = USE_FSR, + }, { + .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00), + .name = "mt25qu01g", + .mfr_flags = USE_FSR, + .fixups = &mt25q01_fixups, }, { .id = SNOR_ID(0x20, 0xbb, 0x21), .name = "n25q00a",