diff mbox series

[v2] KVM: arm64: Only default to enabling SVE when present

Message ID 20231113-kvm-arm64-fp-init-v2-1-98867e5fd97f@kernel.org (mailing list archive)
State New, archived
Headers show
Series [v2] KVM: arm64: Only default to enabling SVE when present | expand

Commit Message

Mark Brown Nov. 13, 2023, 6:09 p.m. UTC
For unclear reasons our handling of SVE and SME when setting the default
value of CPTR_EL2 for VHE mode is inconsistent. For normal VHE we
unconditionally set CPTR_EL2.ZEN to 0b01 but only set the equivalent
field CPTR_EL2.SMEN to 0b01 if SME is present, for hVHE we will always
set the field 0b11 if SVE is not supported. Given the similarities
between the two extensions it would generally be expected that the code
handling SVE and SME would be very similar.

Since CPTR_ELx.ZEN is RES0 when SVE is not implemented it is probably not
harmful to try to set the bits but it is better practice to not set
unimplemented bits so resolve the inconsistency in favour of checking if
SVE is present too.

FPSIMD is also in theory optional though there's probably much more work to
handle the case where it is not implemented properly and that is not
something we see in practical systems.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
Changes in v2:
- Rebase onto v6.7-rc1.
- Link to v1: https://lore.kernel.org/r/20230913-kvm-arm64-fp-init-v1-1-8ce9ba1cc4c4@kernel.org
---
 arch/arm64/include/asm/kvm_emulate.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)


---
base-commit: b85ea95d086471afb4ad062012a4d73cd328fa86
change-id: 20230908-kvm-arm64-fp-init-8948a8d55e44

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
index 78a550537b67..b6f1ddff796c 100644
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -583,15 +583,17 @@  static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu)
 	u64 val;
 
 	if (has_vhe()) {
-		val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN |
-		       CPACR_EL1_ZEN_EL1EN);
+		val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN);
+		if (cpus_have_final_cap(ARM64_SVE))
+			val |= CPACR_EL1_ZEN_EL1EN;
 		if (cpus_have_final_cap(ARM64_SME))
 			val |= CPACR_EL1_SMEN_EL1EN;
 	} else if (has_hvhe()) {
 		val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN);
 
-		if (!vcpu_has_sve(vcpu) ||
-		    (vcpu->arch.fp_state != FP_STATE_GUEST_OWNED))
+		if (cpus_have_final_cap(ARM64_SVE) &&
+		    (!vcpu_has_sve(vcpu) ||
+		     (vcpu->arch.fp_state != FP_STATE_GUEST_OWNED)))
 			val |= CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN;
 		if (cpus_have_final_cap(ARM64_SME))
 			val |= CPACR_EL1_SMEN_EL1EN | CPACR_EL1_SMEN_EL0EN;