From patchwork Mon Nov 13 11:25:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 13453864 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D641C4332F for ; Mon, 13 Nov 2023 11:26:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TxugNWwMccy5xlgirs90NbYIfxFS+8cFYXPZLhG+Jus=; b=cjHoHbUat2GxOv ns5cgxwA2JZgTWzEP6MHMgalp9DPg76KzwPebfEpG0PMKzRQg9zhkjU0L7+Hf66+wCcYe8u8556OW rmh/xEGo+1vb2rmcqSEjGQWCfvPSI1gt3lmK8K1mQoyxtcV+Fv258iXqV184cL4qtK4o7pJdGIksu LVqdwYlLZfE5e4f4c0fU5TjAhES4Q9fCeZe1xJx22vEVTg81VDkxn70cz+a2+b7rEMQtwwwm1cNu8 i14QtUbACCwn6/DtTn6fAcwXBL1J6yVp/tYEKQvDcyJ2M2800wTd1qFffCf2SmuGNVwVaF0YgWvIf PvV4yWM4gJDRswytNXoA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r2V4z-00Djeb-0U; Mon, 13 Nov 2023 11:26:09 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r2V4w-00Djdv-0A for linux-arm-kernel@lists.infradead.org; Mon, 13 Nov 2023 11:26:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A8AAD150C; Mon, 13 Nov 2023 03:26:47 -0800 (PST) Received: from e127643.arm.com (unknown [10.57.71.191]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 191A73F6C4; Mon, 13 Nov 2023 03:25:59 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, suzuki.poulose@arm.com, will@kernel.org, mark.rutland@arm.com Cc: James Clark , Catalin Marinas , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/3] Documentation: arm64: Document the PMU event counting threshold feature Date: Mon, 13 Nov 2023 11:25:06 +0000 Message-Id: <20231113112507.917107-4-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231113112507.917107-1-james.clark@arm.com> References: <20231113112507.917107-1-james.clark@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231113_032606_137085_119F004F X-CRM114-Status: GOOD ( 13.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add documentation for the new Perf event open parameters and the threshold_max capability file. Signed-off-by: James Clark --- Documentation/arch/arm64/perf.rst | 56 +++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/Documentation/arch/arm64/perf.rst b/Documentation/arch/arm64/perf.rst index 1f87b57c2332..36b8111a710d 100644 --- a/Documentation/arch/arm64/perf.rst +++ b/Documentation/arch/arm64/perf.rst @@ -164,3 +164,59 @@ and should be used to mask the upper bits as needed. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c .. _tools/lib/perf/tests/test-evsel.c: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.c + +Event Counting Threshold +========================================== + +Overview +-------- + +FEAT_PMUv3_TH (Armv8.8) permits a PMU counter to increment only on +events whose count meets a specified threshold condition. For example if +threshold_compare is set to 2 ('Greater than or equal'), and the +threshold is set to 2, then the PMU counter will now only increment by +when an event would have previously incremented the PMU counter by 2 or +more on a single processor cycle. + +To increment by 1 after passing the threshold condition instead of the +number of events on that cycle, add the 'threshold_count' option to the +commandline. + +How-to +------ + +The threshold, threshold_compare and threshold_count values can be +provided per event: + +.. code-block:: sh + + perf stat -e stall_slot/threshold=2,threshold_compare=2/ \ + -e dtlb_walk/threshold=10,threshold_compare=3,threshold_count/ + +And the following comparison values are supported: + +.. code-block:: + + 0: Not-equal + 1: Equals + 2: Greater-than-or-equal + 3: Less-than + +The maximum supported threshold value can be read from the caps of each +PMU, for example: + +.. code-block:: sh + + cat /sys/bus/event_source/devices/armv8_pmuv3/caps/threshold_max + + 0x000000ff + +If a value higher than this is given, then it will be silently clamped +to the maximum. The highest possible maximum is 4095, as the config +field for threshold is limited to 12 bits, and the Perf tool will refuse +to parse higher values. + +If the PMU doesn't support FEAT_PMUv3_TH, then threshold_max will read +0, and both threshold and threshold_compare will be silently ignored. +threshold_max will also read as 0 on aarch32 guests, even if the host +is running on hardware with the feature.