From patchwork Fri Nov 17 14:33:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Delaunay X-Patchwork-Id: 13459005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23E9DC197A0 for ; Fri, 17 Nov 2023 14:34:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Vjrsil4FPB2f1DvXdeOaTmju0OfKrFMm9QQk1odUOt8=; b=4RU2Xg8+rY2RLd /Q9tVCBS/d10jaQTCN058tm8hxOUJ5goumlH0vPUKmKl0Se3g0wZyf6nUhphD3QO20pX/ZiO20XFq wcKmWaCGOBvXrTBzClW1HNFsCaFh15GW4LufI5Shi+PnoLcRHgnMPdZVtjRbJRbCq/BusFDp2wSoC dPreVQbM+QX2h5LyB3bAiZu5WvhVd5bC/8EKYv70IwS65pvOQJqYsuAJo9bo1v3J07PYLPjs94Vf7 V0rirnr7/e2KQ1yqU33ldEWIlsYkK8js+qoUaT7HY23B3R+Jtifc4iROcU4qvJOGPW3z0kPyyssKd krOqQJeaiSliPyQPORFw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r3zv6-006kQZ-3D; Fri, 17 Nov 2023 14:34:08 +0000 Received: from mx07-00178001.pphosted.com ([185.132.182.106]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r3zv4-006kP1-1a for linux-arm-kernel@lists.infradead.org; Fri, 17 Nov 2023 14:34:08 +0000 Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3AH9Mg4v015626; Fri, 17 Nov 2023 15:33:53 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=2kptbLSUBCjfzpDr3d+grhLzBCudtePeEMBFobZJJgo=; b=nb 5WDD3paSc2RkhJSUfJJ2/D0CYb3COTreycw9IHutG7jRF4w/xSbj73ZOwamcLVCB L1wNvKb8HBb0SVP9boqYv/bUevAfvPPDMUAN1jighVeMs+erhNXlqv6LxqysSLKB 6qGlc5aQ4cw80s5/Zc3xA9aPacmaUETSvNFsXxpGrFAZhc7V3X6Y5EoUt+r/MF4H 0cMMoT6AQ91PbTXj1qCu4GpxYzAB5dAyOuvC54Q4osREbR/mTHvfHTO7YgPfe35E 8AqqzbM0MA0Lop9FDSqWK53Pxgba215kchdTyuQMf3HQtQNJrr13vONE5iA+clpQ 73mhqBNsdQ+mIrTp67pw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3udn0m4t7s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 15:33:53 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id F26FD100039; Fri, 17 Nov 2023 15:33:48 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id EC6552309C5; Fri, 17 Nov 2023 15:33:48 +0100 (CET) Received: from localhost (10.201.22.165) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 17 Nov 2023 15:33:48 +0100 From: Patrick Delaunay To: Alexandre TORGUE , Srinivas Kandagatla , Maxime Coquelin CC: Patrick Delaunay , , , Subject: [PATCH 2/4] nvmem: stm32: add support for STM32MP25 BSEC to control OTP data Date: Fri, 17 Nov 2023 15:33:35 +0100 Message-ID: <20231117153310.2.I76e50bf760c893b11edfb2ed77388e2939612288@changeid> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231117143338.1173475-1-patrick.delaunay@foss.st.com> References: <20231117143338.1173475-1-patrick.delaunay@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.22.165] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_13,2023-11-17_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231117_063406_865379_DBC91D52 X-CRM114-Status: GOOD ( 13.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On STM32MP25, OTP area may be read/written by using BSEC (boot, security and OTP control). The BSEC internal peripheral is only managed by the secure world. The 12 Kbits of OTP (effective) are organized into the following regions: - lower OTP (OTP0 to OTP127) = 4096 lower OTP bits, bitwise (1-bit) programmable - mid OTP (OTP128 to OTP255) = 4096 middle OTP bits, bulk (32-bit) programmable - upper OTP (OTP256 to OTP383) = 4096 upper OTP bits, bulk (32-bit) programmable, only accessible when BSEC is in closed state. As HWKEY and ECIES key are only accessible by ROM code; only 368 OTP words are managed in this driver (OTP0 to OTP267). This patch adds the STM32MP25 configuration for reading and writing the OTP data using the OP-TEE BSEC TA services. Signed-off-by: Patrick Delaunay --- drivers/nvmem/stm32-romem.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/nvmem/stm32-romem.c b/drivers/nvmem/stm32-romem.c index 8a553b1799a8..82879b1c9eb9 100644 --- a/drivers/nvmem/stm32-romem.c +++ b/drivers/nvmem/stm32-romem.c @@ -269,6 +269,19 @@ static const struct stm32_romem_cfg stm32mp13_bsec_cfg = { .ta = true, }; +/* + * STM32MP25 BSEC OTP: 3 regions of 32-bits data words + * lower OTP (OTP0 to OTP127), bitwise (1-bit) programmable + * mid OTP (OTP128 to OTP255), bulk (32-bit) programmable + * upper OTP (OTP256 to OTP383), bulk (32-bit) programmable + * but no access to HWKEY and ECIES key: limited at OTP367 + */ +static const struct stm32_romem_cfg stm32mp25_bsec_cfg = { + .size = 368 * 4, + .lower = 127, + .ta = true, +}; + static const struct of_device_id stm32_romem_of_match[] __maybe_unused = { { .compatible = "st,stm32f4-otp", }, { .compatible = "st,stm32mp15-bsec", @@ -276,6 +289,9 @@ static const struct of_device_id stm32_romem_of_match[] __maybe_unused = { }, { .compatible = "st,stm32mp13-bsec", .data = (void *)&stm32mp13_bsec_cfg, + }, { + .compatible = "st,stm32mp25-bsec", + .data = (void *)&stm32mp25_bsec_cfg, }, { /* sentinel */ }, };