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17 Nov 2023 18:14:38 +0000 From: Robert Hancock To: "michal.simek@amd.com" , "richard.rojfors@pelagicore.com" , "ben-linux@fluff.org" , "andi.shyti@kernel.org" CC: "linux-arm-kernel@lists.infradead.org" , "linux-i2c@vger.kernel.org" , Robert Hancock Subject: [PATCH 1/2] i2c: xiic: Wait for TX empty to avoid missed TX NAKs Thread-Topic: [PATCH 1/2] i2c: xiic: Wait for TX empty to avoid missed TX NAKs Thread-Index: AQHaGYHtEoEebCqWzEavNcJ8AuRGbQ== Date: Fri, 17 Nov 2023 18:14:38 +0000 Message-ID: <20231117181238.3989861-2-robert.hancock@calian.com> References: <20231117181238.3989861-1-robert.hancock@calian.com> In-Reply-To: <20231117181238.3989861-1-robert.hancock@calian.com> Accept-Language: en-CA, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.42.0 user-agent: Evolution 3.48.4 (3.48.4-1.fc38) x-ms-publictraffictype: Email x-ms-traffictypediagnostic: YT2PR01MB8838:EE_|YQBPR01MB10797:EE_ x-ms-office365-filtering-correlation-id: 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mxYtha7vNHORn+LsI/G6WXwqVMTkgj3o9Aez0wtdqmMN4jAyGN/easa1vp+U4TQPnzU1lpRwGS9jjFukzPKHDr2Pe/2N8g1SKChO1OdclII= X-MS-Exchange-Transport-CrossTenantHeadersStamped: YQBPR01MB10797 X-Proofpoint-GUID: 3KcSas8zGU5-LnbVW65Wo2NuPKDc1mjK X-Proofpoint-ORIG-GUID: 3KcSas8zGU5-LnbVW65Wo2NuPKDc1mjK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_17,2023-11-17_01,2023-05-22_02 X-Proofpoint-Spam-Reason: orgsafe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231117_101452_962280_51434DFF X-CRM114-Status: GOOD ( 17.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Frequently an I2C write will be followed by a read, such as a register address write followed by a read of the register value. In this driver, when the TX FIFO half empty interrupt was raised and it was determined that there was enough space in the TX FIFO to send the following read command, it would do so without waiting for the TX FIFO to actually empty. Unfortunately it appears that in some cases this can result in a NAK that was raised by the target device on the write, such as due to an unsupported register address, being ignored and the subsequent read being done anyway. This can potentially put the I2C bus into an invalid state and/or result in invalid read data being processed. To avoid this, once a message has been fully written to the TX FIFO, wait for the TX FIFO empty interrupt before moving on to the next message, to ensure NAKs are handled properly. Fixes: e1d5b6598cdc ("i2c: Add support for Xilinx XPS IIC Bus Interface") Signed-off-by: Robert Hancock --- drivers/i2c/busses/i2c-xiic.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 71391b590ada..6e84b4d67fd9 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -774,12 +774,15 @@ static irqreturn_t xiic_process(int irq, void *dev_id) xiic_fill_tx_fifo(i2c); - /* current message sent and there is space in the fifo */ - if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { + /* current message fully written */ + if (!xiic_tx_space(i2c)) { dev_dbg(i2c->adap.dev.parent, "%s end of message sent, nmsgs: %d\n", __func__, i2c->nmsgs); - if (i2c->nmsgs > 1) { + /* Don't move onto the next message until the TX FIFO empties, + * to ensure that a NAK is not missed. + */ + if (i2c->nmsgs > 1 && (pend & XIIC_INTR_TX_EMPTY_MASK)) { i2c->nmsgs--; i2c->tx_msg++; xfer_more = 1; @@ -790,11 +793,7 @@ static irqreturn_t xiic_process(int irq, void *dev_id) "%s Got TX IRQ but no more to do...\n", __func__); } - } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) - /* current frame is sent and is last, - * make sure to disable tx half - */ - xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); + } } if (pend & XIIC_INTR_BNB_MASK) {