| Message ID | 20231120070024.4079344-11-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | renesas: rzg3s: Add support for Ethernet | expand |
Hi Claudiu, On Mon, Nov 20, 2023 at 8:01 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add Ethernet nodes available on RZ/G3S (R9A08G045). > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi > @@ -149,6 +149,38 @@ sdhi2: mmc@11c20000 { > status = "disabled"; > }; > > + eth0: ethernet@11c30000 { > + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; > + reg = <0 0x11c30000 0 0x10000>; > + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mux", "fil", "arp_ns"; > + clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, > + <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, > + <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; > + clock-names = "axi", "chi", "refclk"; > + resets = <&cpg R9A08G045_ETH0_RST_HW_N>; > + power-domains = <&cpg>; Perhaps add a default phy mode, like on other SoCs? phy-mode = "rgmii"'; Also missing: #address-cells = <1>; #size-cells = <0>; > + status = "disabled"; > + }; Same comments for eth1. Gr{oetje,eeting}s, Geert
Hi, Geert, On 01.12.2023 19:35, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Mon, Nov 20, 2023 at 8:01 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> >> Add Ethernet nodes available on RZ/G3S (R9A08G045). >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Thanks for your patch! > >> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi >> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi >> @@ -149,6 +149,38 @@ sdhi2: mmc@11c20000 { >> status = "disabled"; >> }; >> >> + eth0: ethernet@11c30000 { >> + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; >> + reg = <0 0x11c30000 0 0x10000>; >> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "mux", "fil", "arp_ns"; >> + clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, >> + <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, >> + <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; >> + clock-names = "axi", "chi", "refclk"; >> + resets = <&cpg R9A08G045_ETH0_RST_HW_N>; >> + power-domains = <&cpg>; > > Perhaps add a default phy mode, like on other SoCs? > > phy-mode = "rgmii"'; I skipped this (even it was available on the other SoCs) as I consider the phy-mode is board specific. > > Also missing: > > #address-cells = <1>; > #size-cells = <0>; Same for these. > >> + status = "disabled"; >> + }; > > Same comments for eth1. > > Gr{oetje,eeting}s, > > Geert >
Hi Claudiu, On Mon, Dec 4, 2023 at 8:41 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote: > On 01.12.2023 19:35, Geert Uytterhoeven wrote: > > On Mon, Nov 20, 2023 at 8:01 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: > >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > >> > >> Add Ethernet nodes available on RZ/G3S (R9A08G045). > >> > >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > > > Thanks for your patch! > > > >> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi > >> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi > >> @@ -149,6 +149,38 @@ sdhi2: mmc@11c20000 { > >> status = "disabled"; > >> }; > >> > >> + eth0: ethernet@11c30000 { > >> + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; > >> + reg = <0 0x11c30000 0 0x10000>; > >> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, > >> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, > >> + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > >> + interrupt-names = "mux", "fil", "arp_ns"; > >> + clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, > >> + <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, > >> + <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; > >> + clock-names = "axi", "chi", "refclk"; > >> + resets = <&cpg R9A08G045_ETH0_RST_HW_N>; > >> + power-domains = <&cpg>; > > > > Perhaps add a default phy mode, like on other SoCs? > > > > phy-mode = "rgmii"'; > > I skipped this (even it was available on the other SoCs) as I consider the > phy-mode is board specific. IC. Still, it's good to have some consistency across boards. > > Also missing: > > > > #address-cells = <1>; > > #size-cells = <0>; > > Same for these. These are required, and always have the same values, so it makes more sense to have them in the SoC .dtsi file, once. Gr{oetje,eeting}s, Geert
On 04.12.2023 10:02, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Mon, Dec 4, 2023 at 8:41 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote: >> On 01.12.2023 19:35, Geert Uytterhoeven wrote: >>> On Mon, Nov 20, 2023 at 8:01 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: >>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >>>> >>>> Add Ethernet nodes available on RZ/G3S (R9A08G045). >>>> >>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >>> >>> Thanks for your patch! >>> >>>> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi >>>> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi >>>> @@ -149,6 +149,38 @@ sdhi2: mmc@11c20000 { >>>> status = "disabled"; >>>> }; >>>> >>>> + eth0: ethernet@11c30000 { >>>> + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; >>>> + reg = <0 0x11c30000 0 0x10000>; >>>> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; >>>> + interrupt-names = "mux", "fil", "arp_ns"; >>>> + clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, >>>> + <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, >>>> + <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; >>>> + clock-names = "axi", "chi", "refclk"; >>>> + resets = <&cpg R9A08G045_ETH0_RST_HW_N>; >>>> + power-domains = <&cpg>; >>> >>> Perhaps add a default phy mode, like on other SoCs? >>> >>> phy-mode = "rgmii"'; >> >> I skipped this (even it was available on the other SoCs) as I consider the >> phy-mode is board specific. > > IC. Still, it's good to have some consistency across boards. > >>> Also missing: >>> >>> #address-cells = <1>; >>> #size-cells = <0>; >> >> Same for these. > > These are required, and always have the same values, so it makes more > sense to have them in the SoC .dtsi file, once. I remember I had a compilation warning with an Ethernet controller configured with fixed-link having #address-cells, #size-cells. With fixed-link these were not needed. Anyway... I'll keep all in dtsi if you prefer it this way. Thank you, Claudiu Beznea > > Gr{oetje,eeting}s, > > Geert >
Hi Claudiu, On Mon, Dec 4, 2023 at 9:38 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote: > On 04.12.2023 10:02, Geert Uytterhoeven wrote: > > On Mon, Dec 4, 2023 at 8:41 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote: > >> On 01.12.2023 19:35, Geert Uytterhoeven wrote: > >>> On Mon, Nov 20, 2023 at 8:01 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: > >>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > >>>> > >>>> Add Ethernet nodes available on RZ/G3S (R9A08G045). > >>>> > >>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > >>> > >>> Thanks for your patch! > >>> > >>>> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi > >>>> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi > >>>> @@ -149,6 +149,38 @@ sdhi2: mmc@11c20000 { > >>>> status = "disabled"; > >>>> }; > >>>> > >>>> + eth0: ethernet@11c30000 { > >>>> + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; > >>>> + reg = <0 0x11c30000 0 0x10000>; > >>>> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, > >>>> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, > >>>> + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > >>>> + interrupt-names = "mux", "fil", "arp_ns"; > >>>> + clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, > >>>> + <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, > >>>> + <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; > >>>> + clock-names = "axi", "chi", "refclk"; > >>>> + resets = <&cpg R9A08G045_ETH0_RST_HW_N>; > >>>> + power-domains = <&cpg>; > >>> > >>> Perhaps add a default phy mode, like on other SoCs? > >>> > >>> phy-mode = "rgmii"'; > >> > >> I skipped this (even it was available on the other SoCs) as I consider the > >> phy-mode is board specific. > > > > IC. Still, it's good to have some consistency across boards. > > > >>> Also missing: > >>> > >>> #address-cells = <1>; > >>> #size-cells = <0>; > >> > >> Same for these. > > > > These are required, and always have the same values, so it makes more > > sense to have them in the SoC .dtsi file, once. > > I remember I had a compilation warning with an Ethernet controller > configured with fixed-link having #address-cells, #size-cells. With > fixed-link these were not needed. I think EtherAVB always use MDIO for management, so fixed-link is not applicable. > Anyway... I'll keep all in dtsi if you prefer it this way. Yes please, thanks! Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 6c7b29b69d0e..1caa0587fdd4 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -149,6 +149,38 @@ sdhi2: mmc@11c20000 { status = "disabled"; }; + eth0: ethernet@11c30000 { + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A08G045_ETH0_RST_HW_N>; + power-domains = <&cpg>; + status = "disabled"; + }; + + eth1: ethernet@11c40000 { + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; + reg = <0 0x11c40000 0 0x10000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>, + <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A08G045_ETH1_RST_HW_N>; + power-domains = <&cpg>; + status = "disabled"; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;