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b=UDh0CHt2GMkrCWpEXX5pLRllckZFyQfIaWicEyAKtZXK3LDmuI2fFru2eXFFsC+0xiQNn+C+wM5LHNj0NureXrbzHrCKg/NYo1mqUEbKz7yBXPgeQuE4CPmv17pr4omlDR/uSoQ0EKvoNTPYrr2+zAXI1oqRQj4sH78Zmvc8NWw= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DB7PR04MB5146.eurprd04.prod.outlook.com (2603:10a6:10:23::16) by VI1PR04MB6880.eurprd04.prod.outlook.com (2603:10a6:803:130::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7025.16; Mon, 20 Nov 2023 09:27:56 +0000 Received: from DB7PR04MB5146.eurprd04.prod.outlook.com ([fe80::709e:6876:7df0:fc30]) by DB7PR04MB5146.eurprd04.prod.outlook.com ([fe80::709e:6876:7df0:fc30%7]) with mapi id 15.20.7025.014; Mon, 20 Nov 2023 09:27:56 +0000 From: Xu Yang To: frank.li@nxp.com, corbet@lwn.net, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: festevam@gmail.com, conor+dt@kernel.org, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, xu.yang_2@nxp.com Subject: [PATCH v3 1/5] perf: fsl_imx8_ddr: Add AXI ID PORT CHANNEL filter support Date: Mon, 20 Nov 2023 17:33:13 +0800 Message-Id: <20231120093317.2652866-1-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 X-ClientProxiedBy: SI1PR02CA0058.apcprd02.prod.outlook.com (2603:1096:4:1f5::9) To DB7PR04MB5146.eurprd04.prod.outlook.com (2603:10a6:10:23::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB7PR04MB5146:EE_|VI1PR04MB6880:EE_ X-MS-Office365-Filtering-Correlation-Id: d0f27763-74d5-4635-e43f-08dbe9aafaaa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0ch9AzUSGH3m/1IPI7K17Akvka16zEg0ZHiqb7GbIiMwYaeOATXOSpiWy4alwTJkEbUu5VapsrECFkUB33iWksSvYi7yv4xmIFjSKrU1xdjRsDRMi3kDnR7bkdiV0f26GsrHq8np4Xr3Md2hlLpqNT148Et3cQwpRb0yAMeYu0UowgjSisVKS16Vwzhqo92sviwLPvFCgb7HIpRavNOgaMfRkOdGGLSTv+mmr8fMHZvSkusaTLwPy3l1XuvvQdC3v1JyBfSkw5mt+sIrnsj8uVpKvJvZJ3TTc15kVFN96+ywBQUjshFWRtPR1aGC8bc+bawXiGrXd+0WChBymIsk4CP8Ai/H6K0+KO1y31Y+hTjDOf8b1R7v78QEke88rK10j2koz4qrq3x2MI25y0KXkJoZbeEbSecPaB69w+h0GQfFY7OlGgRMM0Jpf3Z8og1o5s3z9k1FTrC8ANlIrCB+AXG7h45E0Hh4/BFyrlpR02x3Aj3S2G0DMkaYpzepFmSCnCq6UkZTWmK7U5SxeF4KBVtMFo16frKZjORt2wdm4vBnfIocsyTPRg5wzBYLVamyhZnzniOJGazHUjueuZakXiNpKuculQLk2N0biTWr5P7VhuvasqAXnGOxk4wilqdUeQCedC8ySq4QSfddLx6YGd7J7IjjsClxr6QOod2TH8Eh9pvkMfx6mflX3+4TaEW2brkGybSCkcwCc9Ahcc2Pt2mvR63vwjan7iAzjJkPlG1F8kuWksfLM+L/DRKM1gtqZZpRCOYNWuc4/IVwxDzpj7IHW+xGBG2fz2jwWUHfPNdzsF7DO9pdpeZR61JNVwZTGoERM7JfqQ4rkxfYBBFliCa0s4h4TSmrEvhvXJ1prFwvg6RJQpD8WW/PSQcRxPO6K61cnC5DV2rhZ0ibDPckKL/MhP4sByRpw9foFhNMVR0eiyAy4EmlKg50xF0Nask7CaUzIBsQxWPlADrKa6fryRJ6EKr3TgDsnYq/roacQQBNK+3tFNphVq2X1TtyDnJyJkd2ITSN3I6npxlC+ZoOab3iJX0hNZzJGdqgWrUFHfnuENnVeMYOL4CSNDxprMIWIVXyf9sBIz88j5UtDXthyeK+CTIZwm5ZnKchlKukj1CL72kK+jfH5VrrAnuV6Sf27mM+0LYdJis5LbMp1hz8VFIvG37GSs/Gh9QQNI4lH/EcbpML5agQ347P4sFkmVI/gBVpYu0BwbVvHPjo5S+TB9rgUIJ08ibdda3waRtmM4di8OiKCl0xV6oQrroj931b5WF72VyUC6lHRuM3py50QiN1olQ2BW12aHxnIvgiD7J/4Ybmj1ZBoq0tErQgPoI0feJdiWp+w7So0rudMiTPvd7U1fOA/dOonc2131Jc739yfaMpqhO/QEGIn8MpkKs00/XTsYlx9S0LkmA9KECULGj0t9d/zgNzRJ4umr+IQ3Tsb+ZdHeKMPg0GJQDlcVuw5PE0e1TFoLUN+TJ9YFmkjl6ZSA4YDGRYATRwaONMyrT5X8PZ7mlHWqrKDE4XPFG1LtRLNQxSw9cRWO2yDpHWRnGXhfw+d51GMse/Gh2fq/p/ERv1N7vW8fxae/JeAAcc X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d0f27763-74d5-4635-e43f-08dbe9aafaaa X-MS-Exchange-CrossTenant-AuthSource: DB7PR04MB5146.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2023 09:27:56.5318 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: P0WzgPmsvrPiDw2oA0ku88R7j0YT+lD4tuQlszpF+ejaemWUAZN5ovGEDDvJpd4rwX3wlmmNWP4QNZZSCl9Qyg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6880 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231120_012804_761775_FBEC15A2 X-CRM114-Status: GOOD ( 16.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is the extension of AXI ID filter. Filter is defined with 2 configuration registers per counter 1-3 (counter 0 is not used for filtering and lacks these registers). * Counter N MASK COMP register - AXI_ID and AXI_MASKING. * Counter N MUX CNTL register - AXI CHANNEL and AXI PORT. -- 0: address channel -- 1: data channel This filter is exposed to userspace as an additional (channel, port) pair. The definition of axi_channel is inverted in userspace, and it will be reverted in driver automatically. AXI filter of Perf Monitor in DDR Subsystem, only a single port0 exist, so axi_port is reserved which should be 0. e.g. perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd Signed-off-by: Xu Yang Reviewed-by: Frank Li --- Changes since v2: - no changes Changes since v3: - add Reviewed-by tag --- drivers/perf/fsl_imx8_ddr_perf.c | 39 ++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 92611c98120f..d0eae2d7e64b 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -19,6 +19,8 @@ #define COUNTER_READ 0x20 #define COUNTER_DPCR1 0x30 +#define COUNTER_MUX_CNTL 0x50 +#define COUNTER_MASK_COMP 0x54 #define CNTL_OVER 0x1 #define CNTL_CLEAR 0x2 @@ -32,6 +34,13 @@ #define CNTL_CSV_SHIFT 24 #define CNTL_CSV_MASK (0xFFU << CNTL_CSV_SHIFT) +#define READ_PORT_SHIFT 0 +#define READ_PORT_MASK (0x7 << READ_PORT_SHIFT) +#define READ_CHANNEL_REVERT 0x00000008 /* bit 3 for read channel select */ +#define WRITE_PORT_SHIFT 8 +#define WRITE_PORT_MASK (0x7 << WRITE_PORT_SHIFT) +#define WRITE_CHANNEL_REVERT 0x00000800 /* bit 11 for write channel select */ + #define EVENT_CYCLES_ID 0 #define EVENT_CYCLES_COUNTER 0 #define NUM_COUNTERS 4 @@ -50,6 +59,7 @@ static DEFINE_IDA(ddr_ida); /* DDR Perf hardware feature */ #define DDR_CAP_AXI_ID_FILTER 0x1 /* support AXI ID filter */ #define DDR_CAP_AXI_ID_FILTER_ENHANCED 0x3 /* support enhanced AXI ID filter */ +#define DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER 0x4 /* support AXI ID PORT CHANNEL filter */ struct fsl_ddr_devtype_data { unsigned int quirks; /* quirks needed for different DDR Perf core */ @@ -144,6 +154,7 @@ static const struct attribute_group ddr_perf_identifier_attr_group = { enum ddr_perf_filter_capabilities { PERF_CAP_AXI_ID_FILTER = 0, PERF_CAP_AXI_ID_FILTER_ENHANCED, + PERF_CAP_AXI_ID_PORT_CHANNEL_FILTER, PERF_CAP_AXI_ID_FEAT_MAX, }; @@ -157,6 +168,8 @@ static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap) case PERF_CAP_AXI_ID_FILTER_ENHANCED: quirks &= DDR_CAP_AXI_ID_FILTER_ENHANCED; return quirks == DDR_CAP_AXI_ID_FILTER_ENHANCED; + case PERF_CAP_AXI_ID_PORT_CHANNEL_FILTER: + return !!(quirks & DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER); default: WARN(1, "unknown filter cap %d\n", cap); } @@ -187,6 +200,7 @@ static ssize_t ddr_perf_filter_cap_show(struct device *dev, static struct attribute *ddr_perf_filter_cap_attr[] = { PERF_FILTER_EXT_ATTR_ENTRY(filter, PERF_CAP_AXI_ID_FILTER), PERF_FILTER_EXT_ATTR_ENTRY(enhanced_filter, PERF_CAP_AXI_ID_FILTER_ENHANCED), + PERF_FILTER_EXT_ATTR_ENTRY(super_filter, PERF_CAP_AXI_ID_PORT_CHANNEL_FILTER), NULL, }; @@ -272,11 +286,15 @@ static const struct attribute_group ddr_perf_events_attr_group = { PMU_FORMAT_ATTR(event, "config:0-7"); PMU_FORMAT_ATTR(axi_id, "config1:0-15"); PMU_FORMAT_ATTR(axi_mask, "config1:16-31"); +PMU_FORMAT_ATTR(axi_port, "config2:0-2"); +PMU_FORMAT_ATTR(axi_channel, "config2:3-3"); static struct attribute *ddr_perf_format_attrs[] = { &format_attr_event.attr, &format_attr_axi_id.attr, &format_attr_axi_mask.attr, + &format_attr_axi_port.attr, + &format_attr_axi_channel.attr, NULL, }; @@ -530,6 +548,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) int counter; int cfg = event->attr.config; int cfg1 = event->attr.config1; + int cfg2 = event->attr.config2; if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { int i; @@ -553,6 +572,26 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) return -EOPNOTSUPP; } + if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER) { + if (ddr_perf_is_filtered(event)) { + /* revert axi id masking(axi_mask) value */ + cfg1 ^= AXI_MASKING_REVERT; + writel(cfg1, pmu->base + COUNTER_MASK_COMP + ((counter - 1) << 4)); + + if (cfg == 0x41) { + /* revert axi read channel(axi_channel) value */ + cfg2 ^= READ_CHANNEL_REVERT; + cfg2 |= FIELD_PREP(READ_PORT_MASK, cfg2); + } else { + /* revert axi write channel(axi_channel) value */ + cfg2 ^= WRITE_CHANNEL_REVERT; + cfg2 |= FIELD_PREP(WRITE_PORT_MASK, cfg2); + } + + writel(cfg2, pmu->base + COUNTER_MUX_CNTL + ((counter - 1) << 4)); + } + } + pmu->events[counter] = event; hwc->idx = counter;