| Message ID | 20231120123721.851738-12-maz@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Add support for FEAT_E2H0, or lack thereof | expand |
On 20/11/2023 12:37, Marc Zyngier wrote: > None the Apple M1/M2 CPUs effectively implement E2H=0, and M2 > doesn't correctly implement NV1=1 (the EL2 S1 PTW seems to barf > on the nVHE format). > > Override ID_AA64MMFR4_EL1.E2H0 for these CPUs to reflect what they > actually support. > > Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > arch/arm64/kernel/idreg-override.c | 36 ++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c > index 57c145bf50b7..f7be459e5ff3 100644 > --- a/arch/arm64/kernel/idreg-override.c > +++ b/arch/arm64/kernel/idreg-override.c > @@ -326,7 +326,43 @@ struct midr_override_data { > const struct midr_range ranges[]; > }; > > +static const struct midr_override_data e2h0_ni __initconst = { > + /* > + * These CPUs predate FEAT_E2H0, but have HCR_EL2.E2H RES1 > + * anyway. > + */ > + .feature = "id_aa64mmfr4.e2h0=0xf", > + .ranges = { > + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), > + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), > + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), > + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), > + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), > + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), > + {} > + }, > +}; > + > +static const struct midr_override_data e2h0_nv1_ni __initconst = { > + /* > + * These CPUs predate FEAT_E2H0, but have both HCR_EL2.E2H > + * RES1 and a non-functional HCR_EL2.NV1. > + */ > + .feature = "id_aa64mmfr4.e2h0=0xe", > + .ranges = { > + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), > + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), > + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), > + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), > + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), > + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), > + {} > + }, > +}; > + > static const struct midr_override_data * const midr_ovr_data[] __initconst = { > + &e2h0_ni, > + &e2h0_nv1_ni, > }; > > static void __init apply_midr_overrides(void)
diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c index 57c145bf50b7..f7be459e5ff3 100644 --- a/arch/arm64/kernel/idreg-override.c +++ b/arch/arm64/kernel/idreg-override.c @@ -326,7 +326,43 @@ struct midr_override_data { const struct midr_range ranges[]; }; +static const struct midr_override_data e2h0_ni __initconst = { + /* + * These CPUs predate FEAT_E2H0, but have HCR_EL2.E2H RES1 + * anyway. + */ + .feature = "id_aa64mmfr4.e2h0=0xf", + .ranges = { + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), + {} + }, +}; + +static const struct midr_override_data e2h0_nv1_ni __initconst = { + /* + * These CPUs predate FEAT_E2H0, but have both HCR_EL2.E2H + * RES1 and a non-functional HCR_EL2.NV1. + */ + .feature = "id_aa64mmfr4.e2h0=0xe", + .ranges = { + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), + {} + }, +}; + static const struct midr_override_data * const midr_ovr_data[] __initconst = { + &e2h0_ni, + &e2h0_nv1_ni, }; static void __init apply_midr_overrides(void)
None the Apple M1/M2 CPUs effectively implement E2H=0, and M2 doesn't correctly implement NV1=1 (the EL2 S1 PTW seems to barf on the nVHE format). Override ID_AA64MMFR4_EL1.E2H0 for these CPUs to reflect what they actually support. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kernel/idreg-override.c | 36 ++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)