| Message ID | 20231128045415.210682-3-aford173@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] arm64: dts: imx8mm: Simplify mipi_dsi clocks | expand |
On 28.11.23 05:54, Adam Ford wrote: > Since commit 8208181fe536 ("clk: imx: composite-8m: > Add imx8m_divider_determine_rate") the lcdif controller has > had the ability to set the lcdif_pixel rate which propagates > up the tree and sets the video_pll1 rate automatically. > > By setting this value low, it will force the recalculation of > video_pll1 to the lowest rate needed by lcdif instead of > dividing a larger clock down to the desired clock speed. This > has the advantage of being able to lower the video_pll1 rate > from 594MHz to 148.5MHz when operating at 1080p. It can go even > lower when operating at lower resolutions and refresh rates. > > Signed-off-by: Adam Ford <aford173@gmail.com> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index a3dae114c20e..669fdd2c54e4 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -1131,7 +1131,7 @@ lcdif: lcdif@32e00000 { > assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, > <&clk IMX8MM_SYS_PLL2_1000M>, > <&clk IMX8MM_SYS_PLL1_800M>; > - assigned-clock-rates = <594000000>, <500000000>, <200000000>; > + assigned-clock-rates = <24000000>, <500000000>, <200000000>; > interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; > power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; > status = "disabled"; Thanks for the cleanup! Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index a3dae114c20e..669fdd2c54e4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1131,7 +1131,7 @@ lcdif: lcdif@32e00000 { assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, <&clk IMX8MM_SYS_PLL2_1000M>, <&clk IMX8MM_SYS_PLL1_800M>; - assigned-clock-rates = <594000000>, <500000000>, <200000000>; + assigned-clock-rates = <24000000>, <500000000>, <200000000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; status = "disabled";
Since commit 8208181fe536 ("clk: imx: composite-8m: Add imx8m_divider_determine_rate") the lcdif controller has had the ability to set the lcdif_pixel rate which propagates up the tree and sets the video_pll1 rate automatically. By setting this value low, it will force the recalculation of video_pll1 to the lowest rate needed by lcdif instead of dividing a larger clock down to the desired clock speed. This has the advantage of being able to lower the video_pll1 rate from 594MHz to 148.5MHz when operating at 1080p. It can go even lower when operating at lower resolutions and refresh rates. Signed-off-by: Adam Ford <aford173@gmail.com>