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Sat, 02 Dec 2023 04:52:01 -0800 (PST) Received: from U4.lan ([2a02:810b:f40:4300:908e:b829:354b:f8ee]) by smtp.gmail.com with ESMTPSA id g5-20020a170906198500b009c5c5c2c5a4sm3018161ejd.219.2023.12.02.04.52.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Dec 2023 04:52:00 -0800 (PST) From: Alex Bee To: Heiko Stuebner , Conor Dooley , Krzysztof Kozlowski , Rob Herring Cc: Daniel Vetter , David Airlie , Thomas Zimmermann , Maxime Ripard , Maarten Lankhorst , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Alex Bee Subject: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128 Date: Sat, 2 Dec 2023 13:51:41 +0100 Message-ID: <20231202125144.66052-3-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231202125144.66052-1-knaerzche@gmail.com> References: <20231202125144.66052-1-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231202_045205_771076_FE8AAB80 X-CRM114-Status: GOOD ( 11.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add power controller and qos nodes for RK3128 in order to use them as powerdomains. Signed-off-by: Alex Bee --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 4e8b38604ecd..b72905db04f7 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3128"; @@ -133,6 +134,106 @@ smp-sram@0 { pmu: syscon@100a0000 { compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; reg = <0x100a0000 0x1000>; + + power: power-controller { + compatible = "rockchip,rk3128-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3128_PD_VIO { + reg = ; + clocks = <&cru ACLK_CIF>, + <&cru HCLK_CIF>, + <&cru DCLK_EBC>, + <&cru HCLK_EBC>, + <&cru ACLK_IEP>, + <&cru HCLK_IEP>, + <&cru ACLK_LCDC0>, + <&cru HCLK_LCDC0>, + <&cru PCLK_MIPI>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru ACLK_VIO0>, + <&cru ACLK_VIO1>, + <&cru HCLK_VIO>, + <&cru HCLK_VIO_H2P>, + <&cru DCLK_VOP>, + <&cru SCLK_VOP>; + pm_qos = <&qos_ebc>, + <&qos_iep>, + <&qos_lcdc>, + <&qos_rga>, + <&qos_vip>; + #power-domain-cells = <0>; + }; + + power-domain@RK3128_PD_VIDEO { + reg = ; + clocks = <&cru ACLK_VDPU>, + <&cru HCLK_VDPU>, + <&cru ACLK_VEPU>, + <&cru HCLK_VEPU>, + <&cru SCLK_HEVC_CORE>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3128_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3128_PD_CRYPTO { + reg = ; + clocks = <&cru HCLK_CRYPTO>, + <&cru SCLK_CRYPTO>; + pm_qos = <&qos_crypto>; + #power-domain-cells = <0>; + }; + }; + }; + + qos_crypto: qos@10128080 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x10128080 0x20>; + }; + + qos_gpu: qos@1012d000 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012d000 0x20>; + }; + + qos_vpu: qos@1012e000 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012e000 0x20>; + }; + + qos_rga: qos@1012f000 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f000 0x20>; + }; + + qos_ebc: qos@1012f080 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f080 0x20>; + }; + + qos_iep: qos@1012f100 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f100 0x20>; + }; + + qos_lcdc: qos@1012f180 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f180 0x20>; + }; + + qos_vip: qos@1012f200 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f200 0x20>; }; gic: interrupt-controller@10139000 {