From patchwork Wed Dec 6 10:04:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fuad Tabba X-Patchwork-Id: 13481345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32478C4167B for ; Wed, 6 Dec 2023 10:06:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=0QaBRl7XElZNRJRAqswlgPCLgvOkFRFD+M9MOgd5+BU=; b=vtgSRKoPMqyY/Ig0h0JCBqbk1Y WCxZxSiBM+Kj3r7WyTtTO4isvb6zjBmwpsWIv9Bl3TNl6XKp+VcXHD5PjCt7z8T7DlpxFCToPUrAs vLJ0c705pWRcsi9SC4jJ9J8kMmrD7BnYiL5Yi7aBKkc8wXlysC8MVZ24dhtifXDc9gjV4p8baxfqz B1kmnWEwo0UqCtn/xGEa7SM9fjFKfEOKaLknGeqEUEq/wG6hvxbXlDi9PUgZAhv+nzbcQkLBvoYqU p9qCwIeZiDDIlthNTXEt8GlFtqvSFgQoCZ7oHop2T8GEI0S/gkV6WcLKKCNa5f5i+c/d6upWk+QVS h1TSBF0Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rAomc-009dEi-2x; Wed, 06 Dec 2023 10:05:34 +0000 Received: from mail-yw1-x1149.google.com ([2607:f8b0:4864:20::1149]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rAomX-009d9f-0W for linux-arm-kernel@lists.infradead.org; Wed, 06 Dec 2023 10:05:31 +0000 Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-5d3911218b3so86369087b3.1 for ; Wed, 06 Dec 2023 02:05:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1701857127; x=1702461927; darn=lists.infradead.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=9qLijKD8q5uEfTH/4BglE/UZ689qP1bE0/PcejI4q2w=; b=YWvu9562XYWyQc5Ggis340KHlXvPwS5RDXAukBwOEHXscCrmXpqJJQts+ENORFpwcQ pC9gXaihdMQ6Q990z/Zde84NhecWqa76/sJ6Op8tDlH1i9x34sazW6ag3T6LnBRms4it wOILLtUYlEWMK6x672OPv+zcVGGMa3O5tmhrWGQxW/liNKk1jUbQb3xOZaFRczAZsKYA 3M9/f0joJq8M1IwO6VMi5hdPLow1JxDVGR3mXTT50Ic1MlIlzjAPqsyBLTe8yWeceO2Q 7qwBamrZvMswsg/yGwYdnkhxgL/jtNLnXV6CWn/PHcr36aQuVTyiG/hoKPD6jQPHTw4H O93Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701857127; x=1702461927; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=9qLijKD8q5uEfTH/4BglE/UZ689qP1bE0/PcejI4q2w=; b=aNtZbyufvSlGImylEovhFxcrHCbBXtTedmQBZt42N+tRrUeyjdz04wZ8on/i/bbLCe rKL/GoVUHsRva8pBAhg5vTOl1lLrRM9SXuFyxvZBiSkD4Y/R4ilxGeuiVr0uqdUzQMZ8 G2D417c5nVofgrJowFFcEg0ubQfjhZGDXsgjW4ptXEEM/fIUNuHZcgQdjxLOPCH2H0Oz WdLYcOD3d9v18SU3uYCC0PJdXlUJ174rGih/uTe3IJ+xM4aPCzLpz34N7T8qJpPwQ9vs Z2rglicI0otUD3W53haVjwy1VEZSq21XJpTTizjQeyRVK7U6SZe4pvS3Kf3AwYg3AbYm 7ciA== X-Gm-Message-State: AOJu0Ywqetq2/PYl99QLoQW/nekD/agd/n8nHq4+wsKt6z3IuFZPHyPJ VaRzDK1lRmrJ7RRHeghJ23E9YV3CHA== X-Google-Smtp-Source: AGHT+IHKjvyKeYLrkS5ZZWyHnurnfbOJDHjyqa85gizom7o/uhstJUGb/tajT9c++1MeaHJGxuTLhm2I1A== X-Received: from fuad.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:1613]) (user=tabba job=sendgmr) by 2002:a81:be14:0:b0:5d0:a744:719b with SMTP id i20-20020a81be14000000b005d0a744719bmr7672ywn.0.1701857127610; Wed, 06 Dec 2023 02:05:27 -0800 (PST) Date: Wed, 6 Dec 2023 10:04:59 +0000 In-Reply-To: <20231206100503.564090-1-tabba@google.com> Mime-Version: 1.0 References: <20231206100503.564090-1-tabba@google.com> X-Mailer: git-send-email 2.43.0.rc2.451.g8631bc7472-goog Message-ID: <20231206100503.564090-10-tabba@google.com> Subject: [PATCH v2 09/12] KVM: arm64: Generate the HFGWTR-only RES0 bits From: Fuad Tabba To: kvmarm@lists.linux.dev Cc: maz@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, eric.auger@redhat.com, jingzhangos@google.com, joey.gouly@arm.com, tabba@google.com, linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231206_020529_194443_47EE08D4 X-CRM114-Status: GOOD ( 10.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Generate the HFGWTR-only RES0 bits in sysreg. This is done to consolidate all the bit definitions in one place. No functional change intended. Signed-off-by: Fuad Tabba --- arch/arm64/include/asm/kvm_arm.h | 13 +++---------- arch/arm64/tools/sysreg | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 5b634e909d1c..02442bc90717 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -348,16 +348,9 @@ #define __HFGRTR_EL2_MASK GENMASK(49, 0) #define __HFGRTR_EL2_nMASK (GENMASK(63, 52) | BIT(50)) -/* - * The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any - * future additions, define __HFGWTR* macros relative to __HFGRTR* ones. - */ -#define __HFGxTR_READ_ONLY_MASK (BIT(46) | BIT(42) | BIT(40) | BIT(28) | \ - GENMASK(26, 25) | BIT(21) | BIT(18) | \ - GENMASK(15, 14) | GENMASK(10, 9) | BIT(2)) -#define __HFGWTR_EL2_RES0 (__HFGRTR_EL2_RES0 | __HFGxTR_READ_ONLY_MASK) -#define __HFGWTR_EL2_MASK (__HFGRTR_EL2_MASK & ~__HFGxTR_READ_ONLY_MASK) -#define __HFGWTR_EL2_nMASK (__HFGRTR_EL2_nMASK & ~__HFGxTR_READ_ONLY_MASK) +#define __HFGWTR_EL2_RES0 (__HFGRTR_EL2_RES0 | HFGWTR_ONLY_EL2_RES0) +#define __HFGWTR_EL2_MASK (__HFGRTR_EL2_MASK & ~HFGWTR_ONLY_EL2_RES0) +#define __HFGWTR_EL2_nMASK (__HFGRTR_EL2_nMASK & ~HFGWTR_ONLY_EL2_RES0) #define __HFGITR_EL2_RES0 HFGITR_EL2_RES0 #define __HFGITR_EL2_MASK (BIT(62) | BIT(60) | GENMASK(54, 0)) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index e5631f4e62f4..85f8b385fed2 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2093,6 +2093,32 @@ Field 1 AFSR1_EL1 Field 0 AFSR0_EL1 EndSysregFields +# HFGWTR_EL2 bits are a subset of those for HFGRTR_EL2. +# Define RES0 only present in HFGWTR_EL2. +SysregFields HFGWTR_ONLY_EL2 +Unkn 63:47 +Res0 46 +Unkn 45:43 +Res0 42 +Unkn 41 +Res0 40 +Unkn 39:29 +Res0 28 +Unkn 27 +Res0 26:25 +Unkn 24:22 +Res0 21 +Unkn 20:19 +Res0 18 +Unkn 17:16 +Res0 15:14 +Unkn 13:11 +Res0 10:9 +Unkn 8:3 +Res0 2 +Unkn 1:0 +EndSysregFields + Sysreg HFGRTR_EL2 3 4 1 1 4 Fields HFGxTR_EL2 EndSysreg