From patchwork Wed Dec 6 10:04:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fuad Tabba X-Patchwork-Id: 13481342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB187C10F07 for ; Wed, 6 Dec 2023 10:05:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=sWrPeHoqtyR0Za0s5IuiXXvI0RCz8QT6y81RexjxX8o=; b=Azw9+LWHTpMychwnwGzunUgmnM Mbm79Brg8F8UTpGl3F4z0Oh951YORsecHIjoqn6RorUNkaYgDBgD6jSdXLo1RD+NX7w2SUBJhz94k eboOg3RswuwkFS8KVKHoR+n7j4HfNSrUeqFbZltDT/9MTuK94x7aEuOYhqXB8FNUNoreeY7dJL5Ue Q059ft9Cl3J3BCseVX0L4gZcxxUAdeul7xl1I3098r5tvUy+Z0RXK4xKBx7xrGgAuKTIWri+CAcq1 EMYbylhRDGMgp6jddGHOVHO22XT5zd+KGeWa2SKuUSeBHMte4JwlyERFdSsKcDN2bVrkFzl22jqLf 0iVh8LWA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rAomT-009d82-0w; Wed, 06 Dec 2023 10:05:25 +0000 Received: from mail-wr1-x449.google.com ([2a00:1450:4864:20::449]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rAomP-009d6K-2N for linux-arm-kernel@lists.infradead.org; Wed, 06 Dec 2023 10:05:23 +0000 Received: by mail-wr1-x449.google.com with SMTP id ffacd0b85a97d-33342e25313so554208f8f.3 for ; Wed, 06 Dec 2023 02:05:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1701857120; x=1702461920; darn=lists.infradead.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=pwpiYPnrLh7ZPPeMTHXM6zzGCouwusiFVLcrD3/1XkI=; b=Eygrs8u3FBwfOsmjtY5HQ9ogKzAEPjoZ5uzPgBmjE8aFRO+Ae1gZvAEWuxAr42sTcn NdeZN0UdYqKuQf5V8Tx0nHx3LNshfzuRFU/bYwtE7f3hsEL0HnAslKTmqhHMOzTF7hdD bF4NBdWgXLRv1fwDWY8lH030sY2pL4oaPwlPuk+DJksmldd2b2/WdvQqTe7uRfNCGwU7 rpRLZoDZcOtLn8NaSXzUNsaBN8qFX21HfqLZRX26mZgzdVnteLXqAEwji25ohGHE6S51 qcgLGeTyYG18+N1A90coB1y4AShwcO8AOZh6kQTWFWFrVt1PCPHUVcAfjsjblgGZeaaN gOvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701857120; x=1702461920; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=pwpiYPnrLh7ZPPeMTHXM6zzGCouwusiFVLcrD3/1XkI=; b=MRQ4x2hfOQ/f/E5eb6HqiLLJIr08MX51AnUziKbrotRjlGlDWOZaYhZTjYnLUiAfcU DY+TD+fId1rZ+A9y7XYqOdorHXE4hh8/4yeatScYbyrVTHZunKDXX6v0PctbFpMosoWQ qpYl0BTkcufKI6AI0TFOJTNhVWwDJSu567IlDSal/adSs6l10bz/v5iWdALkHCWu8f3d aCOKsR4o3EaOaxL7qmFLjHF0m2FsSlQ8m7OngWBm/eojBTIrfnND6tvFoNQI3hIbse4h cEhR2ibCPi1C+KzvClkN4K7CFmI/GKvK3RmQySOoLQtgGhAuM+8sG9lZB8m97JUHDy3e QTSg== X-Gm-Message-State: AOJu0Yx4XOZYJwGsBYxy4qj/2h2hhCZYm6MU5J5/Ku9OumMz5DyOjtgn TQoxwsK0hnMmrTEScEdDymRdezEUoA== X-Google-Smtp-Source: AGHT+IERN/r4rU8oOHVmYbqOhtc4WXgg80j7W/v0wLqeViOqqlE24uS8quGxh0Y4vDvK9hfQiIh3Ls9ilA== X-Received: from fuad.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:1613]) (user=tabba job=sendgmr) by 2002:a5d:5d83:0:b0:333:3029:781 with SMTP id ci3-20020a5d5d83000000b0033330290781mr2908wrb.3.1701857120003; Wed, 06 Dec 2023 02:05:20 -0800 (PST) Date: Wed, 6 Dec 2023 10:04:56 +0000 In-Reply-To: <20231206100503.564090-1-tabba@google.com> Mime-Version: 1.0 References: <20231206100503.564090-1-tabba@google.com> X-Mailer: git-send-email 2.43.0.rc2.451.g8631bc7472-goog Message-ID: <20231206100503.564090-7-tabba@google.com> Subject: [PATCH v2 06/12] KVM: arm64: Update and fix FGT register masks From: Fuad Tabba To: kvmarm@lists.linux.dev Cc: maz@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, eric.auger@redhat.com, jingzhangos@google.com, joey.gouly@arm.com, tabba@google.com, linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231206_020521_772266_58C79614 X-CRM114-Status: GOOD ( 12.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org New trap bits have been defined in the 2023-09 Arm Architecture System Registers xml specification [*]. Moreover, the existing definitions of some of the mask and the RES0 bits overlap, which could be wrong, confusing, or both. Update the bits to represent the latest spec (as of this patch, 2023-09), and ensure that the existing bits are consistent. Subsequent patches will use the generated RES0 fields instead of specifying them manually. This patch keeps the manual encoding of the bits to make it easier to review the series. [*] https://developer.arm.com/downloads/-/exploration-tools Fixes: 0fd76865006d ("KVM: arm64: Add nPIR{E0}_EL1 to HFG traps") Signed-off-by: Fuad Tabba --- arch/arm64/include/asm/kvm_arm.h | 39 ++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 7de0a7062625..b0dc3249d5cd 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -344,30 +344,39 @@ * Once we get to a point where the two describe the same thing, we'll * merge the definitions. One day. */ -#define __HFGRTR_EL2_RES0 (GENMASK(63, 56) | GENMASK(53, 51)) +#define __HFGRTR_EL2_RES0 BIT(51) #define __HFGRTR_EL2_MASK GENMASK(49, 0) -#define __HFGRTR_EL2_nMASK (GENMASK(58, 57) | GENMASK(55, 54) | BIT(50)) +#define __HFGRTR_EL2_nMASK (GENMASK(63, 52) | BIT(50)) -#define __HFGWTR_EL2_RES0 (GENMASK(63, 56) | GENMASK(53, 51) | \ - BIT(46) | BIT(42) | BIT(40) | BIT(28) | \ - GENMASK(26, 25) | BIT(21) | BIT(18) | \ +#define __HFGWTR_EL2_RES0 (BIT(51) | BIT(46) | BIT(42) | BIT(40) | \ + BIT(28) | GENMASK(26, 25) | BIT(21) | BIT(18) | \ GENMASK(15, 14) | GENMASK(10, 9) | BIT(2)) -#define __HFGWTR_EL2_MASK GENMASK(49, 0) -#define __HFGWTR_EL2_nMASK (GENMASK(58, 57) | GENMASK(55, 54) | BIT(50)) +#define __HFGWTR_EL2_MASK (GENMASK(49, 47) | GENMASK(45, 43) | \ + BIT(41) | GENMASK(39, 29) | BIT(27) | \ + GENMASK(24, 22) | GENMASK(20, 19) | \ + GENMASK(17, 16) | GENMASK(13, 11) | \ + GENMASK(8, 3) | GENMASK(1, 0)) +#define __HFGWTR_EL2_nMASK (GENMASK(63, 52) | BIT(50)) -#define __HFGITR_EL2_RES0 GENMASK(63, 57) -#define __HFGITR_EL2_MASK GENMASK(54, 0) -#define __HFGITR_EL2_nMASK GENMASK(56, 55) +#define __HFGITR_EL2_RES0 (BIT(63) | BIT(61)) +#define __HFGITR_EL2_MASK (BIT(62) | BIT(60) | GENMASK(54, 0)) +#define __HFGITR_EL2_nMASK GENMASK(59, 55) #define __HDFGRTR_EL2_RES0 (BIT(49) | BIT(42) | GENMASK(39, 38) | \ GENMASK(21, 20) | BIT(8)) -#define __HDFGRTR_EL2_MASK ~__HDFGRTR_EL2_nMASK +#define __HDFGRTR_EL2_MASK (BIT(63) | GENMASK(58, 50) | GENMASK(48, 43) | \ + GENMASK(41, 40) | GENMASK(37, 22) | \ + GENMASK(19, 9) | GENMASK(7, 0)) #define __HDFGRTR_EL2_nMASK GENMASK(62, 59) #define __HDFGWTR_EL2_RES0 (BIT(63) | GENMASK(59, 58) | BIT(51) | BIT(47) | \ BIT(43) | GENMASK(40, 38) | BIT(34) | BIT(30) | \ BIT(22) | BIT(9) | BIT(6)) -#define __HDFGWTR_EL2_MASK ~__HDFGWTR_EL2_nMASK +#define __HDFGWTR_EL2_MASK (GENMASK(57, 52) | GENMASK(50, 48) | \ + GENMASK(46, 44) | GENMASK(42, 41) | \ + GENMASK(37, 35) | GENMASK(33, 31) | \ + GENMASK(29, 23) | GENMASK(21, 10) | \ + GENMASK(8, 7) | GENMASK(5, 0)) #define __HDFGWTR_EL2_nMASK GENMASK(62, 60) #define __HAFGRTR_EL2_RES0 (GENMASK(63, 50) | GENMASK(16, 5)) @@ -375,9 +384,9 @@ #define __HAFGRTR_EL2_nMASK 0UL /* Similar definitions for HCRX_EL2 */ -#define __HCRX_EL2_RES0 (GENMASK(63, 16) | GENMASK(13, 12)) -#define __HCRX_EL2_MASK (0) -#define __HCRX_EL2_nMASK (GENMASK(15, 14) | GENMASK(4, 0)) +#define __HCRX_EL2_RES0 (GENMASK(63, 25) | GENMASK(13, 12)) +#define __HCRX_EL2_MASK (BIT(6)) +#define __HCRX_EL2_nMASK (GENMASK(24, 14) | GENMASK(11, 7) | GENMASK(5, 0)) /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ #define HPFAR_MASK (~UL(0xf))