From patchwork Wed Dec 6 10:04:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fuad Tabba X-Patchwork-Id: 13481347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8B61C10F07 for ; Wed, 6 Dec 2023 10:06:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=WhqCRODQY0iQ/yjDqq1FVGeMSeG+TIp36eKYsc+xJXo=; b=d10dtH7dlb5nTxCKxut6z4nUNF Ed3aaD11m3mI6dU1ajLLsKKc6zaZo5h95iPFNxer6JbWAcT0NTRQv+LCaNMHAb+CZ4xFHVGKntqdn feuTQQck/XwzCsd6j1yUIuzahqT9DlzxSsIT3hanx1x8x7XYjj7yTxMq8VgG8NaOBlFVse4PScqtI ccluHspXoQk2tmtCvelP09sRPeLJ9QOoOUprgPvQMepGWyGQyNYNowtdukSAUlXHN1Ck9s5MnTR6i 22lsCnbF2jsvDgUzA/j6W7guIS+dvGUyixE+348gjPOGZtBm3C/UNYnxXQJa5DiZJ192sH7fAipZP qlpW9KpQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rAomc-009dEK-0P; Wed, 06 Dec 2023 10:05:34 +0000 Received: from mail-yb1-xb49.google.com ([2607:f8b0:4864:20::b49]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rAomW-009d8N-30 for linux-arm-kernel@lists.infradead.org; Wed, 06 Dec 2023 10:05:30 +0000 Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-db9612b8997so3685249276.2 for ; Wed, 06 Dec 2023 02:05:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1701857125; x=1702461925; darn=lists.infradead.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=2TJmXAyMlLq37D84xcPpHxE3ngyDcypNkknRz4uO3sM=; b=xYxyY4IG9ujfrLKDKyCo2JtCkCG9ijV9uXtUfqhRWaIEDs268KL2HVmEKxsSL+m6ka D6+GAlCAVpqW4e3XVarvssqVbd23Sqel3eotpHVF5mge/SE3lQ5pIKfFo1a1IrClfRrR H4g7CjcYS/brUmaVCUG26hE5c/H7qyczRYjrGtgejev0FsnSnxYPeLSi8ZgyCoqMbYej +NE1jK+3Qr8M1S1evThWYhAktWAqEA/a9nbadmalPgrrsAUyfbS61TP2fL460dN4Poqj CYoQpMxVDFfcCoyWRO7ehT/URrx8wBbDxup0oEdByBfwHPZEk9omCHCIVgdDoRZ03wv0 OseQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701857125; x=1702461925; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=2TJmXAyMlLq37D84xcPpHxE3ngyDcypNkknRz4uO3sM=; b=ha9MkL13wObHbZPGoLgKRlsLrdAzxzPNDnHHMrsbHSIrSCU73dKiXsxhaYYtyWrRnZ 3h4zyXntMVicRN/PoV7PFXs+hVFbc+brn+TMn0r9qOOtlZLgccMboL8w3+FMMwuap9TF MLnn5DMPzpfIE/u/Y1zHspLKWBwAIOnDvbPvgCaCeJlu4q/V43PlNKpwiPeUqIKpJEwV xi39rv8LJDeba94CE5p8QG4lZyjrUMDkDvel7sxlkSSAKTeOG7kd6cQ5dUVp2da/YhDu ZBnPsrGZG1zoYai1QZtF+sHUB3O+mJ2EAhPGIxLvkXHJNniEQCPl04Z3auXPVLF+Okbq HZUA== X-Gm-Message-State: AOJu0Yym3GvdYdqAtnX13CdyeD1C+2tauSyxI74hSTz2BEQNJ/wc5+Up 7y2rR9F2pxobOxDIt0u0AApZ/i7nKQ== X-Google-Smtp-Source: AGHT+IEFzffHRskaWLPakpYdzJ6Gt1ONO3k/HVucINukuH87ikK+agwB0OjnhR1n384HG7K/lV8M1+I4bA== X-Received: from fuad.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:1613]) (user=tabba job=sendgmr) by 2002:a25:e0d3:0:b0:d9a:50d2:a8be with SMTP id x202-20020a25e0d3000000b00d9a50d2a8bemr4940ybg.1.1701857125216; Wed, 06 Dec 2023 02:05:25 -0800 (PST) Date: Wed, 6 Dec 2023 10:04:58 +0000 In-Reply-To: <20231206100503.564090-1-tabba@google.com> Mime-Version: 1.0 References: <20231206100503.564090-1-tabba@google.com> X-Mailer: git-send-email 2.43.0.rc2.451.g8631bc7472-goog Message-ID: <20231206100503.564090-9-tabba@google.com> Subject: [PATCH v2 08/12] KVM: arm64: Use generated FGT RES0 bits instead of specifying them From: Fuad Tabba To: kvmarm@lists.linux.dev Cc: maz@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, eric.auger@redhat.com, jingzhangos@google.com, joey.gouly@arm.com, tabba@google.com, linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231206_020528_968179_A9F239EE X-CRM114-Status: GOOD ( 11.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that all FGT fields are accounted for and represented, use the generated value instead of manually specifying them. For __HFGWTR_EL2_RES0, however, there is no generated value. Its fields are subset of HFGRTR_EL2, with the remaining being RES0. Therefore, add a mask that represents the HFGRTR_EL2 only bits and define __HFGWTR_EL2_* using those and the __HFGRTR_EL2_* fields. No functional change intended. Signed-off-by: Fuad Tabba --- arch/arm64/include/asm/kvm_arm.h | 34 +++++++++++++++----------------- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index b0dc3249d5cd..5b634e909d1c 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -344,34 +344,32 @@ * Once we get to a point where the two describe the same thing, we'll * merge the definitions. One day. */ -#define __HFGRTR_EL2_RES0 BIT(51) +#define __HFGRTR_EL2_RES0 HFGxTR_EL2_RES0 #define __HFGRTR_EL2_MASK GENMASK(49, 0) #define __HFGRTR_EL2_nMASK (GENMASK(63, 52) | BIT(50)) -#define __HFGWTR_EL2_RES0 (BIT(51) | BIT(46) | BIT(42) | BIT(40) | \ - BIT(28) | GENMASK(26, 25) | BIT(21) | BIT(18) | \ +/* + * The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any + * future additions, define __HFGWTR* macros relative to __HFGRTR* ones. + */ +#define __HFGxTR_READ_ONLY_MASK (BIT(46) | BIT(42) | BIT(40) | BIT(28) | \ + GENMASK(26, 25) | BIT(21) | BIT(18) | \ GENMASK(15, 14) | GENMASK(10, 9) | BIT(2)) -#define __HFGWTR_EL2_MASK (GENMASK(49, 47) | GENMASK(45, 43) | \ - BIT(41) | GENMASK(39, 29) | BIT(27) | \ - GENMASK(24, 22) | GENMASK(20, 19) | \ - GENMASK(17, 16) | GENMASK(13, 11) | \ - GENMASK(8, 3) | GENMASK(1, 0)) -#define __HFGWTR_EL2_nMASK (GENMASK(63, 52) | BIT(50)) - -#define __HFGITR_EL2_RES0 (BIT(63) | BIT(61)) +#define __HFGWTR_EL2_RES0 (__HFGRTR_EL2_RES0 | __HFGxTR_READ_ONLY_MASK) +#define __HFGWTR_EL2_MASK (__HFGRTR_EL2_MASK & ~__HFGxTR_READ_ONLY_MASK) +#define __HFGWTR_EL2_nMASK (__HFGRTR_EL2_nMASK & ~__HFGxTR_READ_ONLY_MASK) + +#define __HFGITR_EL2_RES0 HFGITR_EL2_RES0 #define __HFGITR_EL2_MASK (BIT(62) | BIT(60) | GENMASK(54, 0)) #define __HFGITR_EL2_nMASK GENMASK(59, 55) -#define __HDFGRTR_EL2_RES0 (BIT(49) | BIT(42) | GENMASK(39, 38) | \ - GENMASK(21, 20) | BIT(8)) +#define __HDFGRTR_EL2_RES0 HDFGRTR_EL2_RES0 #define __HDFGRTR_EL2_MASK (BIT(63) | GENMASK(58, 50) | GENMASK(48, 43) | \ GENMASK(41, 40) | GENMASK(37, 22) | \ GENMASK(19, 9) | GENMASK(7, 0)) #define __HDFGRTR_EL2_nMASK GENMASK(62, 59) -#define __HDFGWTR_EL2_RES0 (BIT(63) | GENMASK(59, 58) | BIT(51) | BIT(47) | \ - BIT(43) | GENMASK(40, 38) | BIT(34) | BIT(30) | \ - BIT(22) | BIT(9) | BIT(6)) +#define __HDFGWTR_EL2_RES0 HDFGWTR_EL2_RES0 #define __HDFGWTR_EL2_MASK (GENMASK(57, 52) | GENMASK(50, 48) | \ GENMASK(46, 44) | GENMASK(42, 41) | \ GENMASK(37, 35) | GENMASK(33, 31) | \ @@ -379,12 +377,12 @@ GENMASK(8, 7) | GENMASK(5, 0)) #define __HDFGWTR_EL2_nMASK GENMASK(62, 60) -#define __HAFGRTR_EL2_RES0 (GENMASK(63, 50) | GENMASK(16, 5)) +#define __HAFGRTR_EL2_RES0 HAFGRTR_EL2_RES0 #define __HAFGRTR_EL2_MASK (GENMASK(49, 17) | GENMASK(4, 0)) #define __HAFGRTR_EL2_nMASK 0UL /* Similar definitions for HCRX_EL2 */ -#define __HCRX_EL2_RES0 (GENMASK(63, 25) | GENMASK(13, 12)) +#define __HCRX_EL2_RES0 HCRX_EL2_RES0 #define __HCRX_EL2_MASK (BIT(6)) #define __HCRX_EL2_nMASK (GENMASK(24, 14) | GENMASK(11, 7) | GENMASK(5, 0))