From patchwork Fri Dec 8 19:45:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 13485836 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59B6AC10DCE for ; Fri, 8 Dec 2023 20:46:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=gp0ciHylgfEuhbRlCIZUjfOckldTuDsnlIP6HlLoytY=; b=HNM5pi0yPRKTtv ZUauK3ObnRjwpK8UYAvAEo0VX38zN8c66YCaYhwbKJ5kg6QnyL1q49e28dTdkUQ0vd0awXjM6jyj8 0FKDnvoP6l5piy/NN/f3AoBmhkMrr28Hud/5enCyGqNlqFLt2Umcd+vnxOndB17XP0ikVDWxAJwOH zYeIJ6RVmvnEKYwXmB9nIA4S/YJrK4qW20yu/cX8BB+tby2YP7baQJOEtxk1k8kXjfwo7N+c98JWw pK3GIJfJygN75jbF5kScxsG6BI1RreF862W1jyfFGPycBdEW4IsJjmbbac+o9tziKPAqWCoOi8Nd5 8O4JKyV7Y3vq1SyU1m4Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rBhjO-00GX6z-07; Fri, 08 Dec 2023 20:45:54 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rBgnC-00GQQr-1L for linux-arm-kernel@lists.infradead.org; Fri, 08 Dec 2023 19:45:48 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1702064746; x=1733600746; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=IroCbTU3D4h208aODf904Dc8f/TADn7N7vXRTCdBR+E=; b=UBQ2tt7m2TzLgaxK7A5BsiMqUfnaNJWR7xvce7dlPwOlz1or4jI+uyTq npAKANRF8MqeWpJzTW8jW6cj2nF7Z431+Tkn2CbPWancqw3bDFm5pDilD 7srnpD9wh/xEMnq6IxCsmK9Df1meEIb8Njsna1ZVgW57CJIvB56yJy1TJ wavWVgk6qWQuouBymlZTH3af5GVhIivHfHxs9M1L0VmwhCuHk8nW5ZQpT c9eCcr1RoPJaZOejVQQLNsgqIiLoMSYl5LR3AQNC7ZO9Vf85VWQLruP1p BqTehqmjw7FrkdyflyCUNQ53ZskMuh12rrj+MFK70sx4cEFsNRjg3uoKU A==; X-CSE-ConnectionGUID: X4oDrwj6SZyrcZeTYIwwlg== X-CSE-MsgGUID: PQnfMIkTSTaeOckEFDgAEA== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.04,261,1695711600"; d="scan'208";a="180178235" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 Dec 2023 12:45:42 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 8 Dec 2023 12:45:12 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 8 Dec 2023 12:45:12 -0700 From: To: , , CC: , , Ryan Wanner Subject: [PATCH v2] drivers: soc: atmel: Adjust defines to follow aphabetical order Date: Fri, 8 Dec 2023 12:45:32 -0700 Message-ID: <20231208194532.579893-1-Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231208_114546_680289_966995BB X-CRM114-Status: UNSURE ( 8.17 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Ryan Wanner Move the defines so that they are in aphabetical order based on SOC. Signed-off-by: Ryan Wanner --- Changes from v1 -> v2: - Remove defines that are not yet in v6.7. drivers/soc/atmel/soc.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 7a9f47ce85fb..1f2af6f74160 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -39,10 +39,10 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9261_CIDR_MATCH 0x019703a0 #define AT91SAM9263_CIDR_MATCH 0x019607a0 #define AT91SAM9G20_CIDR_MATCH 0x019905a0 -#define AT91SAM9RL64_CIDR_MATCH 0x019b03a0 #define AT91SAM9G45_CIDR_MATCH 0x019b05a0 -#define AT91SAM9X5_CIDR_MATCH 0x019a05a0 #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 +#define AT91SAM9RL64_CIDR_MATCH 0x019b03a0 +#define AT91SAM9X5_CIDR_MATCH 0x019a05a0 #define SAM9X60_CIDR_MATCH 0x019b35a0 #define SAMA7G5_CIDR_MATCH 0x00162100 @@ -61,23 +61,15 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9N12_EXID_MATCH 0x00000006 #define AT91SAM9CN11_EXID_MATCH 0x00000009 +#define AT91SAM9XE128_CIDR_MATCH 0x329973a0 +#define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 +#define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 + #define SAM9X60_EXID_MATCH 0x00000000 #define SAM9X60_D5M_EXID_MATCH 0x00000001 #define SAM9X60_D1G_EXID_MATCH 0x00000010 #define SAM9X60_D6K_EXID_MATCH 0x00000011 -#define SAMA7G51_EXID_MATCH 0x3 -#define SAMA7G52_EXID_MATCH 0x2 -#define SAMA7G53_EXID_MATCH 0x1 -#define SAMA7G54_EXID_MATCH 0x0 -#define SAMA7G54_D1G_EXID_MATCH 0x00000018 -#define SAMA7G54_D2G_EXID_MATCH 0x00000020 -#define SAMA7G54_D4G_EXID_MATCH 0x00000028 - -#define AT91SAM9XE128_CIDR_MATCH 0x329973a0 -#define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 -#define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 - #define SAMA5D2_CIDR_MATCH 0x0a5c08c0 #define SAMA5D21CU_EXID_MATCH 0x0000005a #define SAMA5D225C_D1M_EXID_MATCH 0x00000053 @@ -113,6 +105,14 @@ at91_soc_init(const struct at91_soc *socs); #define SAMA5D43_EXID_MATCH 0x00000003 #define SAMA5D44_EXID_MATCH 0x00000004 +#define SAMA7G51_EXID_MATCH 0x3 +#define SAMA7G52_EXID_MATCH 0x2 +#define SAMA7G53_EXID_MATCH 0x1 +#define SAMA7G54_EXID_MATCH 0x0 +#define SAMA7G54_D1G_EXID_MATCH 0x00000018 +#define SAMA7G54_D2G_EXID_MATCH 0x00000020 +#define SAMA7G54_D4G_EXID_MATCH 0x00000028 + #define SAME70Q21_CIDR_MATCH 0x21020e00 #define SAME70Q21_EXID_MATCH 0x00000002 #define SAME70Q20_CIDR_MATCH 0x21020c00 @@ -127,6 +127,11 @@ at91_soc_init(const struct at91_soc *socs); #define SAMS70Q19_CIDR_MATCH 0x211d0a00 #define SAMS70Q19_EXID_MATCH 0x00000002 +#define SAMV70Q20_CIDR_MATCH 0x21320c00 +#define SAMV70Q20_EXID_MATCH 0x00000002 +#define SAMV70Q19_CIDR_MATCH 0x213d0a00 +#define SAMV70Q19_EXID_MATCH 0x00000002 + #define SAMV71Q21_CIDR_MATCH 0x21220e00 #define SAMV71Q21_EXID_MATCH 0x00000002 #define SAMV71Q20_CIDR_MATCH 0x21220c00 @@ -134,9 +139,4 @@ at91_soc_init(const struct at91_soc *socs); #define SAMV71Q19_CIDR_MATCH 0x212d0a00 #define SAMV71Q19_EXID_MATCH 0x00000002 -#define SAMV70Q20_CIDR_MATCH 0x21320c00 -#define SAMV70Q20_EXID_MATCH 0x00000002 -#define SAMV70Q19_CIDR_MATCH 0x213d0a00 -#define SAMV70Q19_EXID_MATCH 0x00000002 - #endif /* __AT91_SOC_H */