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Wed, 13 Dec 2023 11:51:31 -0800 (PST) Received: from U4.lan ([2a02:810b:f40:4300:92dc:8b1c:e01c:b93c]) by smtp.gmail.com with ESMTPSA id fm14-20020a05600c0c0e00b00407b93d8085sm24050698wmb.27.2023.12.13.11.51.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 11:51:31 -0800 (PST) From: Alex Bee To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: David Airlie , Daniel Vetter , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alex Bee Subject: [PATCH 07/11] drm/rockchip: inno_hdmi: Add basic mode validation Date: Wed, 13 Dec 2023 20:51:21 +0100 Message-ID: <20231213195125.212923-8-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231213195125.212923-1-knaerzche@gmail.com> References: <20231213195125.212923-1-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231213_115136_313583_76006064 X-CRM114-Status: GOOD ( 16.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org As per TRM this controller supports pixelclocks starting from 25 MHz. The maximum supported pixelclocks are defined by the phy configurations we have. Also it can't support modes that require doubled clocks. If there is a phy reference clock we can additionally validate against VESA DMT's recommendations. Those checks are added to the mode_valid hook of the connector and encoder's mode_fixup hook. Signed-off-by: Alex Bee --- drivers/gpu/drm/rockchip/inno_hdmi.c | 38 ++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c index f7f0bec725f9..2f839ff31c1c 100644 --- a/drivers/gpu/drm/rockchip/inno_hdmi.c +++ b/drivers/gpu/drm/rockchip/inno_hdmi.c @@ -38,6 +38,8 @@ struct inno_hdmi_variant { struct inno_hdmi_phy_config *default_phy_config; }; +#define INNO_HDMI_MIN_TMDS_CLOCK 25000000U + struct hdmi_data_info { int vic; bool sink_has_audio; @@ -572,6 +574,34 @@ static int inno_hdmi_setup(struct inno_hdmi *hdmi, return 0; } +static enum drm_mode_status inno_hdmi_mode_valid(struct inno_hdmi *hdmi, + struct drm_display_mode *mode) +{ + /* No support for double-clock modes */ + if (mode->flags & DRM_MODE_FLAG_DBLCLK) + return MODE_BAD; + + unsigned int mpixelclk = mode->clock * 1000; + + if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK) + return MODE_CLOCK_LOW; + + if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0) + return MODE_CLOCK_HIGH; + + if (hdmi->refclk) { + long refclk = clk_round_rate(hdmi->refclk, mpixelclk); + unsigned int max_tolerance = mpixelclk / 5000; + + /* Vesa DMT standard mentions +/- 0.5% max tolerance */ + if (abs(refclk - mpixelclk) > max_tolerance || + mpixelclk - refclk > max_tolerance) + return MODE_NOCLOCK; + } + + return MODE_OK; +} + static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) @@ -602,7 +632,9 @@ static bool inno_hdmi_encoder_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, struct drm_display_mode *adj_mode) { - return true; + struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); + + return inno_hdmi_mode_valid(hdmi, adj_mode) == MODE_OK; } static int @@ -659,7 +691,9 @@ static enum drm_mode_status inno_hdmi_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { - return MODE_OK; + struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); + + return inno_hdmi_mode_valid(hdmi, mode); } static int