| Message ID | 20231218110543.64044-2-fusibrandon13@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | cpufreq support for the D1 | expand |
On 12/18/23 05:05, Brandon Cheo Fusi wrote: > Two OPPs are currently defined for the D1/D1s; one at 408MHz and > another at 1.08GHz. Switching between these can be done with the > "sun50i-cpufreq-nvmem" driver. This patch populates the opp table > appropriately, inspired by > https://github.com/Tina-Linux/linux-5.4/blob/master/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi > > The supply voltages are PWM-controlled, but support for that IP > is still in the works. So stick to a target vdd-cpu supply of 0.9V, > which seems to be the default on most D1 boards. > > Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com> > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 64c3c2e6c..2f1771c19 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -39,16 +39,22 @@ cpu0_intc: interrupt-controller { > }; > > opp_table_cpu: opp-table-cpu { > - compatible = "operating-points-v2"; > + compatible = "allwinner,sun20i-d1-operating-points", > + "allwinner,sun50i-h6-operating-points"; This is not correct. The compatible string specifies the algorithm for looking up the speed grade from the NVMEM cell, and D1 uses a totally different algorithm compared to H6: https://github.com/Tina-Linux/linux-5.4/blob/master/drivers/cpufreq/sun50i-cpufreq-nvmem.c#L293-L338 So you cannot use a fallback compatible string here, and you need to add driver support for the D1's speed bin encoding. Regards, Samuel > + nvmem-cells = <&cpu_speed_grade>; > + nvmem-cell-names = "speed"; > + opp-shared; > > opp-408000000 { > + clock-latency-ns = <244144>; /* 8 32k periods */ > opp-hz = /bits/ 64 <408000000>; > - opp-microvolt = <900000 900000 1100000>; > + opp-microvolt-speed0 = <900000 900000 1100000>; > }; > > opp-1080000000 { > + clock-latency-ns = <244144>; /* 8 32k periods */ > opp-hz = /bits/ 64 <1008000000>; > - opp-microvolt = <900000 900000 1100000>; > + opp-microvolt-speed0 = <900000 900000 1100000>; > }; > }; > > @@ -115,3 +121,9 @@ pmu { > <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; > }; > }; > + > +&sid { > + cpu_speed_grade: cpu-speed-grade@0 { > + reg = <0x00 0x2>; > + }; > +};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6c..2f1771c19 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -39,16 +39,22 @@ cpu0_intc: interrupt-controller { }; opp_table_cpu: opp-table-cpu { - compatible = "operating-points-v2"; + compatible = "allwinner,sun20i-d1-operating-points", + "allwinner,sun50i-h6-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed"; + opp-shared; opp-408000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <900000 900000 1100000>; + opp-microvolt-speed0 = <900000 900000 1100000>; }; opp-1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <900000 900000 1100000>; + opp-microvolt-speed0 = <900000 900000 1100000>; }; }; @@ -115,3 +121,9 @@ pmu { <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; }; }; + +&sid { + cpu_speed_grade: cpu-speed-grade@0 { + reg = <0x00 0x2>; + }; +};
Two OPPs are currently defined for the D1/D1s; one at 408MHz and another at 1.08GHz. Switching between these can be done with the "sun50i-cpufreq-nvmem" driver. This patch populates the opp table appropriately, inspired by https://github.com/Tina-Linux/linux-5.4/blob/master/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi The supply voltages are PWM-controlled, but support for that IP is still in the works. So stick to a target vdd-cpu supply of 0.9V, which seems to be the default on most D1 boards. Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com> --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-)