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Thu, 21 Dec 2023 03:50:50 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Dec 2023 19:50:49 -0800 From: Bjorn Andersson Date: Wed, 20 Dec 2023 19:50:35 -0800 Subject: [PATCH 1/8] dt-bindings: clock: qcom: Allow VDD_GFX supply to GX MIME-Version: 1.0 Message-ID: <20231220-sa8295p-gpu-v1-1-d8cdf2257f97@quicinc.com> References: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> In-Reply-To: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Ulf Hansson , Johan Hovold , "Catalin Marinas" , Will Deacon CC: , , , , , , "Bjorn Andersson" X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703130649; l=841; i=quic_bjorande@quicinc.com; s=20230915; h=from:subject:message-id; bh=gsLSzEtTNvvjs9aLDTb4B3w5KFCxmior5IC60emfAk4=; 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Allow this to be described in the GPU clock controller binding. Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,gpucc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index f369fa34e00c..013ef78d2b31 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -53,6 +53,9 @@ properties: power-domains: maxItems: 1 + vdd-gfx-supply: + description: Regulator supply for the VDD_GFX pads + '#clock-cells': const: 1