Message ID | 20231220135722.192080-3-angelogioacchino.delregno@collabora.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | MediaTek DRM - DSI driver cleanups | expand |
Hi Angelo, On Wed, Dec 20, 2023 at 9:57 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote: > > Function mtk_dsi_ps_control() is a subset of mtk_dsi_ps_control_vact(): > merge the two in one mtk_dsi_ps_control() function by adding one > function parameter `config_vact` which, when true, writes the VACT > related registers. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 76 +++++++++--------------------- > 1 file changed, 23 insertions(+), 53 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > index 23d2c5be8dbb..b618e2e31022 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -352,40 +352,6 @@ static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) > mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); > } > > -static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) > -{ > - struct videomode *vm = &dsi->vm; > - u32 dsi_buf_bpp, ps_wc; > - u32 ps_bpp_mode; > - > - if (dsi->format == MIPI_DSI_FMT_RGB565) > - dsi_buf_bpp = 2; > - else > - dsi_buf_bpp = 3; > - > - ps_wc = vm->hactive * dsi_buf_bpp; > - ps_bpp_mode = ps_wc; > - > - switch (dsi->format) { > - case MIPI_DSI_FMT_RGB888: > - ps_bpp_mode |= PACKED_PS_24BIT_RGB888; > - break; > - case MIPI_DSI_FMT_RGB666: > - ps_bpp_mode |= PACKED_PS_18BIT_RGB666; > - break; > - case MIPI_DSI_FMT_RGB666_PACKED: > - ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666; > - break; > - case MIPI_DSI_FMT_RGB565: > - ps_bpp_mode |= PACKED_PS_16BIT_RGB565; > - break; > - } > - > - writel(vm->vactive, dsi->regs + DSI_VACT_NL); > - writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); > - writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); > -} > - > static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) > { > u32 tmp_reg; > @@ -417,36 +383,40 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) > writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); > } > > -static void mtk_dsi_ps_control(struct mtk_dsi *dsi) > +static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact) > { > - u32 dsi_tmp_buf_bpp; > - u32 tmp_reg; > + struct videomode *vm = &dsi->vm; > + u32 dsi_buf_bpp, ps_wc; > + u32 ps_bpp_mode; > + > + if (dsi->format == MIPI_DSI_FMT_RGB565) > + dsi_buf_bpp = 2; > + else > + dsi_buf_bpp = 3; The same is also in mtk_dsi_config_vdo_timing(). Given this is a cleanup series, I think it'd be a good chance to add another patch and integrate those usages. Just a thought. :) > > + > + ps_wc = vm->hactive * dsi_buf_bpp; I noticed the "& DSI_PS_WC" part was dropped (but perhaps with awareness?). While the outcome seems to always fall within the range of DSI_PS_WC so we should be fine in practice, I think it doesn't hurt to keep the value masked to save readers some time to check if this would ever be possible to overflow and write undesired bits down the line. WDYT? Regardless of that, I didn't find obvious issue in this patch, so Reviewed-by: Fei Shao <fshao@chromium.org> Regards, Fei > > + ps_bpp_mode = ps_wc; > > switch (dsi->format) { > case MIPI_DSI_FMT_RGB888: > - tmp_reg = PACKED_PS_24BIT_RGB888; > - dsi_tmp_buf_bpp = 3; > + ps_bpp_mode |= PACKED_PS_24BIT_RGB888; > break; > case MIPI_DSI_FMT_RGB666: > - tmp_reg = LOOSELY_PS_18BIT_RGB666; > - dsi_tmp_buf_bpp = 3; > + ps_bpp_mode |= PACKED_PS_18BIT_RGB666; > break; > case MIPI_DSI_FMT_RGB666_PACKED: > - tmp_reg = PACKED_PS_18BIT_RGB666; > - dsi_tmp_buf_bpp = 3; > + ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666; > break; > case MIPI_DSI_FMT_RGB565: > - tmp_reg = PACKED_PS_16BIT_RGB565; > - dsi_tmp_buf_bpp = 2; > - break; > - default: > > - tmp_reg = PACKED_PS_24BIT_RGB888; > - dsi_tmp_buf_bpp = 3; > + ps_bpp_mode |= PACKED_PS_16BIT_RGB565; > break; > } > > - tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC; > > - writel(tmp_reg, dsi->regs + DSI_PSCTRL); > + if (config_vact) { > + writel(vm->vactive, dsi->regs + DSI_VACT_NL); > + writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); > + } > + writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); > } > > static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) > @@ -522,7 +492,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) > writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); > writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); > > - mtk_dsi_ps_control(dsi); > + mtk_dsi_ps_control(dsi, false); > } > > static void mtk_dsi_start(struct mtk_dsi *dsi) > @@ -667,7 +637,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); > > - mtk_dsi_ps_control_vact(dsi); > + mtk_dsi_ps_control(dsi, true); > mtk_dsi_set_vm_cmd(dsi); > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > -- > 2.43.0 > >
Il 26/12/23 11:48, Fei Shao ha scritto: > Hi Angelo, > > On Wed, Dec 20, 2023 at 9:57 PM AngeloGioacchino Del Regno > <angelogioacchino.delregno@collabora.com> wrote: >> >> Function mtk_dsi_ps_control() is a subset of mtk_dsi_ps_control_vact(): >> merge the two in one mtk_dsi_ps_control() function by adding one >> function parameter `config_vact` which, when true, writes the VACT >> related registers. >> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> --- >> drivers/gpu/drm/mediatek/mtk_dsi.c | 76 +++++++++--------------------- >> 1 file changed, 23 insertions(+), 53 deletions(-) >> >> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c >> index 23d2c5be8dbb..b618e2e31022 100644 >> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c >> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c >> @@ -352,40 +352,6 @@ static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) >> mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); >> } >> >> -static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) >> -{ >> - struct videomode *vm = &dsi->vm; >> - u32 dsi_buf_bpp, ps_wc; >> - u32 ps_bpp_mode; >> - >> - if (dsi->format == MIPI_DSI_FMT_RGB565) >> - dsi_buf_bpp = 2; >> - else >> - dsi_buf_bpp = 3; >> - >> - ps_wc = vm->hactive * dsi_buf_bpp; >> - ps_bpp_mode = ps_wc; >> - >> - switch (dsi->format) { >> - case MIPI_DSI_FMT_RGB888: >> - ps_bpp_mode |= PACKED_PS_24BIT_RGB888; >> - break; >> - case MIPI_DSI_FMT_RGB666: >> - ps_bpp_mode |= PACKED_PS_18BIT_RGB666; >> - break; >> - case MIPI_DSI_FMT_RGB666_PACKED: >> - ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666; >> - break; >> - case MIPI_DSI_FMT_RGB565: >> - ps_bpp_mode |= PACKED_PS_16BIT_RGB565; >> - break; >> - } >> - >> - writel(vm->vactive, dsi->regs + DSI_VACT_NL); >> - writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); >> - writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); >> -} >> - >> static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) >> { >> u32 tmp_reg; >> @@ -417,36 +383,40 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) >> writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); >> } >> >> -static void mtk_dsi_ps_control(struct mtk_dsi *dsi) >> +static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact) >> { >> - u32 dsi_tmp_buf_bpp; >> - u32 tmp_reg; >> + struct videomode *vm = &dsi->vm; >> + u32 dsi_buf_bpp, ps_wc; >> + u32 ps_bpp_mode; >> + >> + if (dsi->format == MIPI_DSI_FMT_RGB565) >> + dsi_buf_bpp = 2; >> + else >> + dsi_buf_bpp = 3; > > The same is also in mtk_dsi_config_vdo_timing(). Given this is a > cleanup series, I think it'd be a good chance to add another patch > and integrate those usages. Just a thought. :) Checking that right now. >> >> + >> + ps_wc = vm->hactive * dsi_buf_bpp; > > I noticed the "& DSI_PS_WC" part was dropped (but perhaps with awareness?). > > While the outcome seems to always fall within the range of > DSI_PS_WC so we should be fine in practice, I think it doesn't hurt to > keep the value masked to save readers some time to check if this would > ever be possible to overflow and write undesired bits down the line. > WDYT? > Masking a pre-masked value doesn't look right. Besides, as for the concern of overflowing, if we masked that we'd still end up with broken functionality, as if the value is invalid... well, it's invalid. Masked or not. :-) Thanks for the R-b, sending a v3 soon with some fixes. Regards, Angelo > Regardless of that, I didn't find obvious issue in this patch, so > > Reviewed-by: Fei Shao <fshao@chromium.org> > > Regards, > Fei > > > > >> >> + ps_bpp_mode = ps_wc; >> >> switch (dsi->format) { >> case MIPI_DSI_FMT_RGB888: >> - tmp_reg = PACKED_PS_24BIT_RGB888; >> - dsi_tmp_buf_bpp = 3; >> + ps_bpp_mode |= PACKED_PS_24BIT_RGB888; >> break; >> case MIPI_DSI_FMT_RGB666: >> - tmp_reg = LOOSELY_PS_18BIT_RGB666; >> - dsi_tmp_buf_bpp = 3; >> + ps_bpp_mode |= PACKED_PS_18BIT_RGB666; >> break; >> case MIPI_DSI_FMT_RGB666_PACKED: >> - tmp_reg = PACKED_PS_18BIT_RGB666; >> - dsi_tmp_buf_bpp = 3; >> + ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666; >> break; >> case MIPI_DSI_FMT_RGB565: >> - tmp_reg = PACKED_PS_16BIT_RGB565; >> - dsi_tmp_buf_bpp = 2; >> - break; >> - default: >> >> - tmp_reg = PACKED_PS_24BIT_RGB888; >> - dsi_tmp_buf_bpp = 3; >> + ps_bpp_mode |= PACKED_PS_16BIT_RGB565; >> break; >> } >> >> - tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC; >> >> - writel(tmp_reg, dsi->regs + DSI_PSCTRL); >> + if (config_vact) { >> + writel(vm->vactive, dsi->regs + DSI_VACT_NL); >> + writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); >> + } >> + writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); >> } >> >> static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) >> @@ -522,7 +492,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) >> writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); >> writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); >> >> - mtk_dsi_ps_control(dsi); >> + mtk_dsi_ps_control(dsi, false); >> } >> >> static void mtk_dsi_start(struct mtk_dsi *dsi) >> @@ -667,7 +637,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) >> mtk_dsi_reset_engine(dsi); >> mtk_dsi_phy_timconfig(dsi); >> >> - mtk_dsi_ps_control_vact(dsi); >> + mtk_dsi_ps_control(dsi, true); >> mtk_dsi_set_vm_cmd(dsi); >> mtk_dsi_config_vdo_timing(dsi); >> mtk_dsi_set_interrupt_enable(dsi); >> -- >> 2.43.0 >> >>
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 23d2c5be8dbb..b618e2e31022 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -352,40 +352,6 @@ static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); } -static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) -{ - struct videomode *vm = &dsi->vm; - u32 dsi_buf_bpp, ps_wc; - u32 ps_bpp_mode; - - if (dsi->format == MIPI_DSI_FMT_RGB565) - dsi_buf_bpp = 2; - else - dsi_buf_bpp = 3; - - ps_wc = vm->hactive * dsi_buf_bpp; - ps_bpp_mode = ps_wc; - - switch (dsi->format) { - case MIPI_DSI_FMT_RGB888: - ps_bpp_mode |= PACKED_PS_24BIT_RGB888; - break; - case MIPI_DSI_FMT_RGB666: - ps_bpp_mode |= PACKED_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB666_PACKED: - ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB565: - ps_bpp_mode |= PACKED_PS_16BIT_RGB565; - break; - } - - writel(vm->vactive, dsi->regs + DSI_VACT_NL); - writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); - writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); -} - static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) { u32 tmp_reg; @@ -417,36 +383,40 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); } -static void mtk_dsi_ps_control(struct mtk_dsi *dsi) +static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact) { - u32 dsi_tmp_buf_bpp; - u32 tmp_reg; + struct videomode *vm = &dsi->vm; + u32 dsi_buf_bpp, ps_wc; + u32 ps_bpp_mode; + + if (dsi->format == MIPI_DSI_FMT_RGB565) + dsi_buf_bpp = 2; + else + dsi_buf_bpp = 3; + + ps_wc = vm->hactive * dsi_buf_bpp; + ps_bpp_mode = ps_wc; switch (dsi->format) { case MIPI_DSI_FMT_RGB888: - tmp_reg = PACKED_PS_24BIT_RGB888; - dsi_tmp_buf_bpp = 3; + ps_bpp_mode |= PACKED_PS_24BIT_RGB888; break; case MIPI_DSI_FMT_RGB666: - tmp_reg = LOOSELY_PS_18BIT_RGB666; - dsi_tmp_buf_bpp = 3; + ps_bpp_mode |= PACKED_PS_18BIT_RGB666; break; case MIPI_DSI_FMT_RGB666_PACKED: - tmp_reg = PACKED_PS_18BIT_RGB666; - dsi_tmp_buf_bpp = 3; + ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666; break; case MIPI_DSI_FMT_RGB565: - tmp_reg = PACKED_PS_16BIT_RGB565; - dsi_tmp_buf_bpp = 2; - break; - default: - tmp_reg = PACKED_PS_24BIT_RGB888; - dsi_tmp_buf_bpp = 3; + ps_bpp_mode |= PACKED_PS_16BIT_RGB565; break; } - tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC; - writel(tmp_reg, dsi->regs + DSI_PSCTRL); + if (config_vact) { + writel(vm->vactive, dsi->regs + DSI_VACT_NL); + writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); + } + writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); } static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) @@ -522,7 +492,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); - mtk_dsi_ps_control(dsi); + mtk_dsi_ps_control(dsi, false); } static void mtk_dsi_start(struct mtk_dsi *dsi) @@ -667,7 +637,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_reset_engine(dsi); mtk_dsi_phy_timconfig(dsi); - mtk_dsi_ps_control_vact(dsi); + mtk_dsi_ps_control(dsi, true); mtk_dsi_set_vm_cmd(dsi); mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi);
Function mtk_dsi_ps_control() is a subset of mtk_dsi_ps_control_vact(): merge the two in one mtk_dsi_ps_control() function by adding one function parameter `config_vact` which, when true, writes the VACT related registers. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/gpu/drm/mediatek/mtk_dsi.c | 76 +++++++++--------------------- 1 file changed, 23 insertions(+), 53 deletions(-)