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Wysocki" , Viresh Kumar , Stephen Rothwell Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Brandon Cheo Fusi Subject: [RFC PATCH v2 2/3] cpufreq: sun50i: Add support for D1's speed bin decoding Date: Thu, 21 Dec 2023 11:10:12 +0100 Message-Id: <20231221101013.67204-3-fusibrandon13@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20231221101013.67204-1-fusibrandon13@gmail.com> References: <20231221101013.67204-1-fusibrandon13@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231221_021054_863835_1C06206D X-CRM114-Status: GOOD ( 14.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds support for decoding the efuse value read from D1 efuse speed bins, and factors out equivalent code for sun50i. The algorithm is gotten from https://github.com/Tina-Linux/linux-5.4/blob/master/drivers/cpufreq/sun50i-cpufreq-nvmem.c#L293-L338 and maps an efuse value to either 0 or 1, with 1 meaning stable at a lower supply voltage for the same clock frequency. Signed-off-by: Brandon Cheo Fusi --- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c index fc509fc49..b1cb95308 100644 --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c @@ -29,6 +29,33 @@ struct sunxi_cpufreq_data { u32 (*efuse_xlate)(u32 *speedbin, size_t len); }; +static u32 sun20i_efuse_xlate(u32 *speedbin, size_t len) +{ + u32 ret, efuse_value = 0; + int i; + + for (i = 0; i < len; i++) + efuse_value |= ((u32)speedbin[i] << (i * 8)); + + switch (efuse_value) { + case 0x5e00: + /* QFN package */ + ret = 0; + break; + case 0x5c00: + case 0x7400: + /* QFN package */ + ret = 1; + break; + case 0x5000: + default: + /* BGA package */ + ret = 0; + } + + return ret; +} + static u32 sun50i_efuse_xlate(u32 *speedbin, size_t len) { u32 efuse_value = 0; @@ -46,6 +73,10 @@ static u32 sun50i_efuse_xlate(u32 *speedbin, size_t len) return 0; } +struct sunxi_cpufreq_data sun20i_cpufreq_data = { + .efuse_xlate = sun20i_efuse_xlate, +}; + struct sunxi_cpufreq_data sun50i_cpufreq_data = { .efuse_xlate = sun50i_efuse_xlate, }; @@ -54,6 +85,9 @@ static const struct of_device_id cpu_opp_match_list[] = { { .compatible = "allwinner,sun50i-h6-operating-points", .data = &sun50i_cpufreq_data, }, + { .compatible = "allwinner,sun20i-d1-operating-points", + .data = &sun20i_cpufreq_data, + }, {} };