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Wysocki" , Viresh Kumar , Stephen Rothwell Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Brandon Cheo Fusi Subject: [RFC PATCH v2 3/3] riscv: dts: allwinner: Fill in OPPs Date: Thu, 21 Dec 2023 11:10:13 +0100 Message-Id: <20231221101013.67204-4-fusibrandon13@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20231221101013.67204-1-fusibrandon13@gmail.com> References: <20231221101013.67204-1-fusibrandon13@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231221_021100_242565_4861E22C X-CRM114-Status: UNSURE ( 9.49 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Specify two voltage ranges, in order of increasing stability, for each OPP. Link: https://github.com/Tina-Linux/linux-5.4/blob/master/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi#L118-L133 Link: https://github.com/mangopi-sbc/tina-linux-5.4/blob/0d4903ebd9d2194ad914686d5b0fc1ddacf11a9d/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi#L118-L182 Signed-off-by: Brandon Cheo Fusi --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6c..7e2e015e0 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -39,16 +39,23 @@ cpu0_intc: interrupt-controller { }; opp_table_cpu: opp-table-cpu { - compatible = "operating-points-v2"; + compatible = "allwinner,sun20i-d1-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed"; + opp-shared; opp-408000000 { opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <900000 900000 1100000>; + + opp-microvolt-speed0 = <950000 950000 1100000>; + opp-microvolt-speed1 = <900000 900000 1100000>; }; opp-1080000000 { opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <900000 900000 1100000>; + + opp-microvolt-speed0 = <1100000>; + opp-microvolt-speed1 = <950000 950000 1100000>; }; }; @@ -115,3 +122,9 @@ pmu { <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; }; }; + +&sid { + cpu_speed_grade: cpu-speed-grade@0 { + reg = <0x00 0x2>; + }; +};