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Thu, 21 Dec 2023 13:45:12 +0100 (CET) Received: from localhost (10.252.25.159) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 21 Dec 2023 13:45:12 +0100 From: Raphael Gallais-Pou To: Laurent Pinchart , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Yannick Fertre , Raphael Gallais-Pou , Philippe Cornu , Philipp Zabel , Lad Prabhakar , Thierry Reding CC: , , , , Subject: [PATCH RESEND v1 5/8] drm/stm: ltdc: add lvds pixel clock Date: Thu, 21 Dec 2023 13:43:36 +0100 Message-ID: <20231221124339.420119-6-raphael.gallais-pou@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231221124339.420119-1-raphael.gallais-pou@foss.st.com> References: <20231221124339.420119-1-raphael.gallais-pou@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.25.159] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-21_06,2023-12-20_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231221_044537_969313_51567DB2 X-CRM114-Status: GOOD ( 15.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The STM32MP25x display subsystem presents a mux which feeds the loopback pixel clock of the current bridge in use into the LTDC. This mux is only accessible through sysconfig registers which is not yet available in the STM32MP25x common clock framework. While waiting for a complete update of the clock framework, this would allow to use the LVDS. Signed-off-by: Raphael Gallais-Pou Signed-off-by: Yannick Fertre --- drivers/gpu/drm/stm/ltdc.c | 18 ++++++++++++++++++ drivers/gpu/drm/stm/ltdc.h | 1 + 2 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 67064f47a4cb..1cf9f16e56cc 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -838,6 +838,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc, int target_max = target + CLK_TOLERANCE_HZ; int result; + if (ldev->lvds_clk) { + result = clk_round_rate(ldev->lvds_clk, target); + DRM_DEBUG_DRIVER("lvds pixclk rate target %d, available %d\n", + target, result); + } + result = clk_round_rate(ldev->pixel_clk, target); DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); @@ -1898,6 +1904,8 @@ void ltdc_suspend(struct drm_device *ddev) clk_disable_unprepare(ldev->pixel_clk); if (ldev->bus_clk) clk_disable_unprepare(ldev->bus_clk); + if (ldev->lvds_clk) + clk_disable_unprepare(ldev->lvds_clk); } int ltdc_resume(struct drm_device *ddev) @@ -1918,6 +1926,12 @@ int ltdc_resume(struct drm_device *ddev) return -ENODEV; } } + if (ldev->lvds_clk) { + if (clk_prepare_enable(ldev->lvds_clk)) { + DRM_ERROR("Unable to prepare lvds clock\n"); + return -ENODEV; + } + } return 0; } @@ -1989,6 +2003,10 @@ int ltdc_load(struct drm_device *ddev) } } + ldev->lvds_clk = devm_clk_get(dev, "lvds"); + if (IS_ERR(ldev->lvds_clk)) + ldev->lvds_clk = NULL; + rstc = devm_reset_control_get_exclusive(dev, NULL); mutex_init(&ldev->err_lock); diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index 155d8e4a7c6b..662650a0fae2 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -44,6 +44,7 @@ struct ltdc_device { void __iomem *regs; struct regmap *regmap; struct clk *pixel_clk; /* lcd pixel clock */ + struct clk *lvds_clk; /* lvds pixel clock */ struct clk *bus_clk; /* bus clock */ struct mutex err_lock; /* protecting error_status */ struct ltdc_caps caps;